Toshiba, Infineon detail plans for 32-Mbit FeRAM

Toshiba, Infineon detail plans for 32-Mbit FeRAM
TOKYO — Ferroelectric RAM partners Infineon Technologies AG and Toshiba Corp. are developing a capacitor-on-plug (COP) design that will take the non-volatile memory to 128-Mbit densities, the partners said.

The companies plan to ship evaluation chips of a 32-Mbit FeRAM late this year and to achieve mass production of that device in 2003, said Shizuo Sawada, group manager of the advanced memory device group at Toshiba Semiconductor Co. The 32-Mbit FeRAM is of sufficient density to begin replacing the SRAM and flash chip combination commonly used in today's cell phones, the companies said.

Furthermore, the design can be feasibly scaled to the 64-Mbit density, and a further doubling in density can also be achieved, said Christian Scheibe, project manager of Infineon's FeRAM development team based at Toshiba's research and development center in Yokohama, Japan.

"We have some ideas for the 64-Mbit and the 128-Mbit densities, and according to our data, we think we can easily use our current concept to get there," Scheibe said. "But beyond that we may have to adopt different approaches, for example 3D."

Toshiba has brought to the partnership its lead zirconate titanate (PZT) material, and a single-transistor, single-capacitor design. Infineon contributed an approach that prevents metal contamination. The companies have been working together on FeRAM since December 2000.

FeRAM's appeal is in a combination of features that includes the endurance of DRAM, the fast read/write times of SRAM and the non-volatility of flash. But it poses challenges as well: megabit densities are hindered by large cell sizes, additional process steps are required for manufacturing PZT capacitors and ferroelectric materials are by nature unstable. Scheibe said the Infineon-Toshiba alliance has chosen to use strontium ruthenium oxide and is successfully working through the deposition process to improve FeRAM's lifetime reliability.

Given the thicket of design and manufacturing issues blocking FeRAM's path, many companies aim the high reliability parts at niche, low-density applications.

A major FeRAM breakthrough in recent years was the development of single-transistor, single-capacitor cells, which led to a slew of new products. Fujitsu Ltd., for example, is perfecting a 1-Mbit design that strips out the FeRAM's fuse ROM and adds multiple redundant circuits. And NEC Corp. expects to embed a 1-Mbit FeRAM cell on a smart card controller. Ramtron International Corp., an FeRAM pioneer, recently announced a 3-volt, 256-kbit part with an endurance specification of at least 10 quadrillion read/write cycles with full data retention.

Scaling beyond the 1-Mbit density is problematic for standard FeRAM designs that use bulky, space-wasting offset capacitors. That's one reason why Samsung Electronics Co. Ltd. and the Toshiba-Infineon team are taking the COP approach, which uses a DRAM-like design that places a capacitor directly on top of a transistor. Samsung, for example, has announced that it is developing a 4-Mbit FeRAM cell using a COP approach.

But the COP design is also problematic. It uses iridium, iridium oxide compounds and special adhesives to create barriers to protect transistors through the production process. The payoff is a dramatic improvement in density.

COP advantages

Later this summer, Infineon and Toshiba will sample a 3-V, 8-Mbit cell that uses PZT ferroelectric material and strontium ruthenium oxide electrodes in a standard offset approach that achieve 50-ns to 80-ns write access times in a die measuring 5.2 microns². But a combination of Toshiba's chain FeRAM design layout with the COP approach will yield a 32-Mbit part with write access times of 35 ns to 50 ns and cell sizes measuring about 1.9 microns², according to data sheets that Infineon and Toshiba are showing customers.

"Using Toshiba's chain FeRAM design and then adding the COP approach means we have two advantages," said Scheibe. First, the 32-Mbit parts will beat the duo's 8-Mbit parts that appear later this year in nearly every parameter except size. The 8-Mbit part will occupy 76 square millimeters, and the 32-Mbit part will occupy about 100 square millimeters, according to data sheets. Second, the write and read cycle times will be 70-to-100 ns on the 32-Mbit part, compared to 100-to-160 ns on the 8-Mbit part.

"The 8-meg was the first stage and not for production," Sawada said. "But using COP we can make the cells much denser for production."

Infineon and Toshiba are accelerating their schedule for the 32-Mbit part, moving the parts to a 0.20-micron process instead of a 0.25-micron process, as originally planned. Other fine-tuning includes moving from two to three metal layers to reduce the overhead for items such as drivers.

While the companies press on, Toshiba has clear plans to put FeRAM to work in mobile phones, said Satoshi Shinozaki, vice president of Toshiba Semiconductor's memory division.

"Ferroelectric RAMs have faster data read and write times than flash memory and can be easily embedded in logic circuits," Shinozaki said. "As they meet all the essentials for system LSI, integrating memory and logic circuits on a single chip, we expect ferroelectric RAM to become the key LSI memory technology.

"We are positioning FeRAM as a price-competitive solution and expect ferroelectric RAM to eventually replace low-density, multi-chip SRAM and NOR [flash] packages," Shinozaki said.