Custom vs. ASIC, part 2

Custom vs. ASIC, part 2
I went across town a couple of weeks ago to Alchemy Semiconductor, where Rich Witek, Greg Hoeppner and other members of the former Austin-based StrongARM design team now work. As the Brits say, they are beavering away on a MIPS-based system-on-chip that claims to offer the best of both worlds: It is portable, yet it offers good performance and power metrics. Call it a semi-portable custom design.

The interview at Alchemy reminded me of an unfinished task. Our EDA editor, Richard Goering, had asked me to cover a panel discussion at the Design Automation Conference in June, "Bridging the gap between full-custom and ASIC design," that proved fascinating.

To start things off, Berkeley professor Kurt Keutzer and Bill Daly of Stanford presented work-based on research by graduate students D.G. Chinnery and Andrew Chang, respectively-that is worth a look. (If you have the DAC 2000 proceedings in your library, see pages 637-647. If you don't, I will try to fax the pages to you for your personal use. You can reach the profs at keutzer@eecs. berkeley.edu and billd@cva.stanford.edu).

Keutzer and Chinnery compared quarter-micron designs completed in both full-custom and ASIC design styles, and found a six- to eight-times speed difference between the two. The factors contributing to that difference ranged from the most important-the ability to architect a custom design with heavy pipelining and few logic levels between registers-to a series of lesser ones: the optimization in custom designs of floor planning and placement, resizing wires and transistors, and the use of dynamic logic on critical paths. Also, since ASIC processes must guarantee a wide latitude, Keutzer claimed that designing to a specific process can be almost twice as fast as targeting a commercial ASIC process.

Daly followed with an equally impassioned argument that ASIC designs need not lag so far behind custom. Pointing to wires as the main culprits, he argued that designers should be able to turn normal procedures on their head: laying out the wiring first to ensure relatively short wires throughout, and then placing transistors afterwards. And he called on EDA vendors to come up with new ASIC design tools that could give ASIC designers better control over the physical design.

"If the design fails to meet power and timing goals after place and route and after repowering the cells along the critical paths it is very difficult to to fix the problem by changing the RTL," said Daly. "It is very frustrating when the solution [structuring the wiring] is obvious, but there is no way to tell the tools how to do it."