NewPort unveils Sonet transceivers

NewPort unveils Sonet transceivers
IRVINE, Calif. — Two years ago, NewPort Communications Inc. said its unique CMOS design would let the company develop integrated transceivers at both 2.5- and 10-Gbit/second Sonet rates. This week, at NetWorld+Interop, the company will show working product from both efforts: production single-chip transceivers for 2.5-Gbit networks that use quarter-micron CMOS, and engineering samples of 10-Gbit transmitter/receiver pairs that use 0.18-micron CMOS.

Joe Vithayathil, vice president of sales and marketing at NewPort, said that even the physical-layer specialists who talk of CMOS for OC-48 (2.5-Gbit/s) Sonet usually must resort to 0.18-micron processes for such transceivers. NewPort will move to 0.18-micron for transceivers that add additional channels or added functionality, but will use 0.25-micron CMOS for its workhorse transceiver, the NP2510.

The NP2510 is a fully integrated transceiver with on-chip clock generator based on a phase-locked loop, a clock and data recovery unit, and a 16-bit 155-MHz interface compatible with low-voltage PECL processes. All data and clock lines in the chip use emitter-coupled logic capable of driving 50-ohm loads.

For 10-Gbit networks, NewPort elected to begin with a pair of devices, the NP1010 transmitter with 16:1 multiplexer, and the NP1011 receiver with 1:16 demultiplexer. This pair of devices uses a 0.18-micron process and a suite of proprietary design methods developed under NewPort's Current-Controlled CMOS (C3MOS) methodology, but Vithayathil said that further work with the designs should allow an integrated transceiver to be produced in a 0.18-micron process.

The demonstrations at N+I should shake up quite a few assumptions in the physical transceiver world.

Applied Microcircuits Corp. has hitched its wagon to silicon germanium processes, while Vitesse Semiconductor Corp. is moving to indium phosphide for 10 Gbits and above. Giga Inc., meanwhile, is sampling some early 10-Gbit CMOS devices, but may be delayed in its design effort by its imminent acquisition by Intel Corp.

Beyond CMOS

Because NewPort has numerous patents pending regarding its C3MOS design methodology, NewPort only describes the method as "allowing efficient ways to get best f_T out of a device using the least amount of real estate," Vithayathil said. What is important to recognize, he said, is that the C3MOS methods could be applied to other process technologies outside CMOS, such as silicon germanium or III-V compounds.

Meanwhile, NewPort will be able to convert its more-mature high-speed designs from C3MOS to static MOS designs. Thus, the company is wedded neither to CMOS implementations nor to its C3MOS method, but will look for the most cost-effective and lowest-power means to develop a range of high-speed transceivers.

Those transceivers eventually will cover 1-Gbit and 10-Gigabit Ethernet as well as Sonet. Since the OC-48 and OC-192 products emerging from NewPort this year meet all relevant Bellcore and International Telecommunication Union jitter specs for Sonet, Ethernet-based designs with looser bit-error tolerance will be easy to derive from the original transceiver designs, Vithayathil said.

The NP1010/1011 pair offers several milestones in Sonet design besides the CMOS makeup. The chips dissipate a combined 1.3 watts in a typical line card. The core circuitry uses a 1.8-volt power supply, and can work with interfaces at 1.8 V, 2.5 V or 3.3 V. Both the transmitter and the receiver use low-voltage differential-swing interfaces at 622 Mbits/s.

The NP1010 includes a 16 x 9 FIFO on the chip to eliminate system timing problems as well as an integrated clock multiplier capable of using 155- or 622-MHz external references.

The 1:16 demux on the NP1011 is tied directly through output registers to a 16-bit parallel LVDS interface. Clock recovery in the 1011 receiver device is performed through synchronizing the on-chip voltage-controlled oscillator to the incoming data stream.

The NP2510 is in production now, in a 128-pin plastic quad flat pack, at a 100-piece price of $245 each. The NP1010 and NP1011, both in 116-pin ball-grid array, are in early sampling. General sampling will begin in September, when pricing will be announced, followed by full production in the fourth quarter.