Xilinx adds Internet-based design reuse tools

Xilinx adds Internet-based design reuse tools
SAN JOSE, Calif. — FPGA vendor Xilinx Inc. will expand on its Xpresso Internet-based design effort this week by launching its Silicon Xpresso Design Reuse Initiative, which aims to help Xilinx customers implement design-for-reuse practices and to share cores internally.

The company will offer two tools free from the Xilinx Web site to aid customers in packaging internal intellectual property (IP) for use in Xilinx's Core Generator tool. Xilinx is also offering a supplement to the Reuse Methodology Manual to help designers enhance design-for-reuse practices so designs can be implemented in FPGA architectures in addition to ASIC architectures.

"Customers like Cisco Systems and Nortel have hundreds if not thousands of engineers creating designs and, effectively, creating IP," said Rich Sevcik, senior vice president of software, cores and support at Xilinx. "We are creating tools that will allow designers to capture their own IP, put it into the Core Generator and then share it with other engineers within their company."

Xilinx's two new tools, IP Internet Capture and IP Remote Interface, work in conjunction with Xilinx's Core Generator, an IP catalog and core generation tool.

Jim Burnham, product marketing manager at Xilinx, said Internet Capture allows Xilinx customers to package their own IP and place it on their corporate intranet or the Internet, where it can be accessed using Core Generator. The IP Remote Interface goes a step further, and makes cores parameterizable.

"Core Generator develops two types of cores: fixed function cores and parameterizable," said Burnham. "Predominantly those cores have come from Xilinx and our Alliance Core [program] partners. Now, with these tools, we are extending that flow to our customers so they can capture and catalog their own IP."

In the Xilinx scheme of things, designers are prompted by IP Internet Capture to identify fixed-function IP files such as HDL source modules, net-lists or simulation files. The designer then inputs IP documentation such as PDF data sheets or Web pages. A prompt requests core data such as behavioral models and simulation vectors. It also requests core descriptions and support contact information, and asks users to identify supported output file targets.

Zip or wrap

"The tool requires entry of support materials, so it helps enforce companies' design-reuse standards," said Burnham.

IP Internet Capture then zips or wraps the core with Xilinx install and writes a Web page. "When the designer is done they have zipped up the file and Web page," said Burnham. "They can post that on their intranet or put it in an internal companywide catalog. They can also store and download the cores with the Core Generator."

For parameterization, Burnham said, designers can use the IP Remote Interface tool interactively to write their own GUI and executables for each core, assuming the core's HDL is written in a parameterizable-friendly manner. The user creates executables and defines whether the core can be generated from a set of fixed net-lists, by modifying generic values in VHDL or Verilog source, or driven by algorithmic code implemented in programming languages such as Perl, C++ or Java. It also provides security and controls access to IP source code, which can be encrypted or compiled.

Sevcik said the tool will likely be used by large customers that are a step ahead of designing for reuse, and are designing for parameterizability. "Alcatel is a company that started about a year ago to do this," said Sevcik.

In addition, the company is also releasing "Xilinx Design Reuse Methodology for ASIC and FPGA Designers." The 27 page supplement to the Reuse Methodology Manual (RMM), which was co-authored by designers from Mentor Graphics and Synopsys, intends to encourage designers to refine design-reuse practices so their designs can be targeted to FPGAs as well as ASICs.

The manual points out system-level reuse issues for FPGAs, provides coding and synthesis tips, and offers guidance on building a verification strategy. Burnham said the supplement has drawn good reviews from the authors of the RMM and their companies.

The IP Internet Capture and IP Remote Interface can be downloaded free, but users must have version 2.1I of Xilinx Alliance and Foundation software, which contains the Core Generator software, to use them.