IP99: Designers see little need to move away from HDLs

IP99: Designers see little need to move away from HDLs
EDINBURGH, Scotland — Hardware engineers are happy with VHDL and Verilog and are not eager to move away from hardware description languages to new higher level languages, according to a straw poll taken at a panel session at the IP99 Europe conference.

In a session titled, "Is synthesizable C coming soon?" Jim Cardwell, vice president of marketing and sales at Cynapps Inc. (Santa Clara, Calif.), asked an audience of about 200 how many were experienced in designing at the register transfer level with HDLs. About 125 hands went up. But when Cardwell asked how many wanted to move to another language all but one or two of the hands shot down.

While academics and managers at semiconductor, EDA and systems companies seem to agree that the electronics design industry needs to move up to a higher level of abstraction, it seems that hardware engineers will have to be dragged and cosseted into any new era of system-on-chip (SoC) design.

One observer said he was not surprised at the unanimity of the engineers' response. "These people are experts in VHDL and Verilog, their skills are in high demand because of the design productivity gap and their salaries are rising. Why would they want to see a change?"

But attendance at the panel suggested that engineers were at least interested in learning more about design from high-level languages. "They voted one way with their hands and another way with their feet," the observer said.

The panel, moderated by Larry Rosenberg, chairman of the technical committee of the Virtual Socket Interface Alliance (VSIA), concluded that synthesizable C is not only coming soon but is available now. But the key issue is what sort of synthesis is available and how useful it is, the panel concluded.

Paul Rosenfeld, director of business development at CoWare Inc. (Santa Clara, Calif.), pitched for "a common dialect" of C/C++ to allow the industry to progress, and he referenced the Open SystemC Initiative that his company has recently launched with Synopsys Inc.

Simon Davidmann, president and chief executive officer of Co-Design Automation Inc. (San Jose, Calif.), voiced concerns over attempts to push designers towards C/C++ as the next design entry language. "With class libraries you end up with a roll-your-own simulation environment," he said. "C is a software programming language so you can write anything in C you want to, but the users are all going in different directions."

Davidmann then briefly described his company's Superlog language as the appropriate solution. Superlog is a purpose-built language that takes the best features of C, Verilog and VHDL to craft the "first viable SoC language," Davidmann said.

Philip Dworsky, marketing and applications manager in the design reuse group at Synopsys (Mountain View, Calif.), spoke last and reiterated claims of multi-company support for the SystemC initiative. Although it only offers modeling support at present, SystemC is moving towards broader capabilities in synthesis, he said.

One audience member asked how any moves to new languages addressed the fact that system, hardware and software engineers are different and have different backgrounds, training and cultures.

Panelists responded by discussing the trend of RTL engineers moving up in abstraction and systems engineers moving down, and said a new language could bridge the gap between specification and implementation. But none of the panelists was prepared to address what seemed to be the underlying premise of the panel: that such a partitioned organization might be today's reality, but is a thing of the past.