SH5 from Hitachi, STMicro runs two instruction sets

SH5 from Hitachi, STMicro runs two instruction sets
SAN JOSE, Calif. — Hitachi Ltd. and STMicroelectronics Inc. will unveil this week the latest version of the SuperH processor architecture. The two companies have been collaborating on this generation, the SH5, for two years, and the design is the architecture's first major revamp since the original SH1 was launched in 1992.

The SH5 is both a new product and a revision of its predecessor, the SH4. In order to maintain compatibility, the new version uses the same instruction set as the earlier SuperH chips, but also uses an entirely new instruction set to deliver higher performance. An on-board switching engine allows the core to use the older coding for basic tasks, and reserves the newer code for more complicated functions.

"This allows us to completely revamp the design, but [make it] still compatible with all the legacy applications that are using the earlier SH products," said Greville Commins, director of U.S. operations for ST's micro products group. ST and Hitachi will jointly present the design this week at the Microprocessor Forum technology conference here.

The SH5 features a seven-stage pipeline, compared with the five stages used in earlier versions. It also takes the SH family from a 32-bit to a 64-bit device. While each instruction is longer, the single-issue architecture only processes one instruction at a time. "We think this is the best way to design a processor, the best way to increase performance," said Jim Slager, director of advanced microprocessor core development for Hitachi Semiconductor (America) Inc.

400-MHz and more

The initial SH5 products will run at 400 MHz, although Slager said later versions will reach 650 MHz. The two companies have collaborated on both the architecture and on a new manufacturing process that both will own.

The SH5 will be produced at the 0.15-micron level, using copper interconnect technology, and will run on 1.5 volts. The core is 14 square millimeters. It has a floating-point unit, but can be produced without it. Slager said that combination of performance, power consumption and die size will make the SH5 a solid entry in the world of embedded processors.

"This is targeted at a variety of applications, including digital cameras and set-top boxes, communications and networking systems, and home networks and handheld consumer devices," said Peter Carbone, SuperH product marketing manager for Hitachi.

The core will sample in the fourth quarter of next year, and should ramp early in 2001. Both Hitachi and ST will produce their own chips using the core, and they will split royalty revenue from licensing the core. The two companies would not disclose whether they are dividing those sums evenly.

In addition to a new instruction set, the SH5 also features a new, high-speed internal bus, termed the SuperHyway. It runs at 200 MHz and delivers up to 3.2 Gbytes/second of peak bandwidth. The bus is used within the new core, while many of the peripheral blocks that are held over from previous SH versions and do not require high bandwidth, will still use the preceding bus architecture, the P bus. "Everything outside the new core runs slower," said Slager. "There's no reason to run these things any faster, and that just uses extra power."

As part of the new instructions, the SH5 uses a split-branch implementation. Slager said that allows for a more efficient use of the longer pipeline.

"Using both instruction sets is a clever idea," said Tom Halfhill, embedded-processor analyst for MicroDesign Resources (Sunnyvale, Calif.). He agreed that it allows for both backward compatibility and a forward-looking, higher-performance design, noting that the legacy code will likely run as fast, or even faster, on the SH5, because it has been scaled down to the 0.15-micron level. Meanwhile, some of the older instructions will get translated to utilize the new coding. "I think this is a good approach. It looks pretty good to me," Halfhill said.