Hyperchip taps ARC cores for peta router offerings

Hyperchip taps ARC cores for peta router offerings
MONTREAL — Hyperchip Inc. has chosen the ARC Cores Ltd. 32-bit core generator architecture to create a HyperMatrix chip that the company claims will achieve unprecedented speeds in router architectures.

Hyperchip started life pursuing wafer-scale processing strategies for the development of merchant interconnect chips, but has recently focused on using its HyperMatrix design to develop its own "peta routers," which chief technology officer Richard Norman called the next step for backbone services, going beyond tera-router offerings from such companies as Nexabit Inc. (now part of Lucent) and Pluris Inc.

The HyperMatrix design, which has 32 cores configured as "transmitters" in a crosspoint matrix, is one of the most ambitious for a reconfigurable RISC core used as a network processor. Norman said Hyperchip had developed prototypes of its future router using 16 large Xilinx field-programmable gate arrays (FPGAs), and had considered turning to ASICs, standalone network processors or embedded cores. ARC Cores won because its notion of synthesizable core generators was what Hyperchip needed for creating a flexible device like HyperMatrix.

"An FPGA could not be used in the final device," Norman said. "The main datapath device must be implemented in hard logic."

Norman stressed that the switching matrix is only one-half of the Hyperchip solution. The company is in the early phase of developing a design for a line card with 5-Gbit/second capabilities for carrying quad Gigabit Ethernet or single OC-48 services. The line card would use an I/O-intensive network processor from ARC Cores or one of several other contenders being considered.

In the Hyperchip design, most first-pass traffic-shaping and quality-of-service assignments would be performed by the line-card processor. By the time packets are assigned to the HyperMatrix, only very simple packet-forwarding decisions need to be made at each ARC node, allowing the chip to achieve speeds not seen to date, according to Norman.

Prior to founding Hyperchip two years ago, Norman had worked on 3-D virtual reality engines for an entertainment hardware startup. Many of the processing concepts were carried over from that project. He earlier was involved in advanced research with IBM Microelectronics. Norman pulled together a team that included executives from LSI Logic, Mosaid and Nortel Networks.

Critics examining pipelined multichannel devices, or pattern engines that reduce packet search spaces, have questioned whether Hyperchip's degree of on-chip parallelism will prove either implementable or cost-effective. Norman predicted the company could beat other router architectures to market by the time wave-division multiplexing sends backbone speeds to 40 Gbits/s and above. In fact, the option of interface directly to WDM equipment would be intriguing, Norman said.