Startups stake out turf in network processor battle

Startups stake out turf in network processor battle
ATLANTA — In the aftermath of back-to-back network processor announcements from IBM Microelectronics and Intel Corp., startups in the network processor space say they aren't worried about being overshadowed here at this week's Networld+Interop show.

The consensus is that if the Intel announcement and IBM product are to make their mark through the sheer size of their providers, it will be years from now, when commoditization gives rise to a low-end network-processor market. For now, the startups — which focus almost exclusively on high-end switching in the network backbone — believe their rarified technology is enough of a calling card to propel them out of IBM's and Intel's reach.

Meanwhile, the startups are trying to show viability for net processor architectures still in the early stages of OEM acceptance. Agere Inc. (Austin, Texas), pulling ahead of much of the pack, is already sampling its second chip, the Route Switch Processor. And Hyperchip Inc. is quietly nailing down details of its processor architecture, for which it will use ARC cores.

Advancements in fiber optics, particularly the advent of wave-division multiplexing, have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, it's "at the crossing points, the nodes of the network," where traffic is intercepted or forwarded, said Michel Desbard, chairman and chief executive of T.sqware Inc. (Santa Clara, Calif.).

Hence the flood of interest in speeding those nodes, making the equipment run faster by means of specialized chips to handle data trafficking. "Network processor" is the blanket name thrown over such chips in their varied forms.

Intel's IXP1200 will compete with IBM's Rainier part as well as processors from C-Port Corp., SiTera Inc., MMC Networks Inc. and others. All of the offerings handle packet processing in the network backbone, speeding packets of data to the proper destinations.

The network processor market is in its early stages, where fancy technology holds more sway than marketing or brand names. And for the WAN market being chased by nearly all network-processor startups, even price becomes secondary to performance or even raw speed. The primary interest in the backbone is to shuttle packets as quickly as possible.

Although the thought of competing with behemoths like Intel and IBM may seem daunting, "there's plenty of space for new suppliers and new concepts" in the network processor space, said Bob Merritt, an analyst with Semico Research Corp.

"Protocols are constantly changing, and data rates are increasing at a phenomenal pace," Merritt said. "RISC processors are not doubling in speed every year the way data rates are, which is why people are looking at other constructions.

"Some of these designs are aimed at Internet service pro-viders handling large amounts of data; some are aimed at wide-area networking switching and routing. Given that we don't know how the protocol issues will settle down, there will be an opportunity for a number of people to come in and make a contribution."

Most startups agree that there's room for multiple success stories, and to that end, most claim they won't be competing directly with Intel or IBM.

Bob Bridge, Agere's vice president of marketing, claimed that the linking of some of the fielded network processors to specific CPUs will keep his company's more-agnostic approach from competing directly with offerings from C-Port, Maker Communications Inc. and Intel. Instead, the Fast Pattern Processor and Route Switch Processor chips from Agere will run up against the MMC network processor and upcoming distributed engines from Vitesse Semiconductor subsidiary Xaqti Corp.

Agere, one of the few network processor startups to move to full sampling of its pattern-processing engine, is ratcheting competition to the next level by sampling the second element in its two-pronged strategy, the Route Switch Processor. Bridge said that the addition of a queue management engine to Agere's existing Fast Pattern Processor should give the young company a leg up on network processors more dependent on a local host CPU.

Concurrent with sampling of the Route Switch Processor, Agere has signed pacts with Power X Ltd. (Manchester, England) to link the FPP chip directly to Power X's TeraChannel switching fabric chip set. Agere also has an agreement with Inverness Systems Inc. (Marlborough, Mass.) under which Inverness will provide source code modules for the Agere architecture, starting with a software module for multiprotocol label switching.

Other startups similarly claim advantages that set them apart from the pack.

T.sqware claims to be the only company building network processors for edge devices — the routers and switches that collect and prepare packets obtained from the LAN and then shoot them into the backbone over a high-speed line. The specialty here is in software, because an effective network processor on the edge has to be able to work with multiple types of incoming traffic, said Desbard.

"For those guys [IBM and Intel] to do the same thing, they'd need to acquire this software competence," Desbard said. Because the raw speed requirements of the backbone make a simpler play, he doesn't expect to see serious competition from either chip heavyweight anytime soon.

"The issues at the backbone are not the same as the issues on the edge," he said.

Similar feelings were expressed by Wade Appelman, vice president of marketing for SiTera (Longmont, Colo.). Rather than different players driving each other to ruin, he sees the market stratifying into high- and low-end needs, as happened with network switches. SiTera hopes to play in the high end of that stratified market, while Appelman sees Intel, IBM and others consigned to the low end.

Maintaining speeds

"Everybody's going to the least common denominator of how many processors can you put in your chip. That's not where the battle is going to be," Appelman said. The battle will be in maintaining high switching speeds while also providing advanced features, he said, because services slow down a network's performance significantly.

SiTera, accordingly, has concentrated on maintaining processing speed even for packets that require heavy attention from the network.

And given that customers are the likes of Cisco — whose end markets aren't in the consumer space — there's plenty of opportunity for sophisticated technology to win out over marketing muscle, Appelman said. If that's the case, it defuses one of IBM's and particularly Intel's most potent threats.

"Maybe five or 10 years from now it'll be different," Appelman said, "but it's not going to be marketing that's going to win this debate. It's the ability to solve unique problems."

Andy Gottlieb, vice president of marketing for MMC (Sunnyvale, Calif.), offered a variation on that theme. "The whole market [for network processors is] growing very fast," he noted. "We can all grow without getting into each other's markets, because we're competing with internal ASICs."

As for Intel, the switch fabric provided by Acclaim — owned by Intel acquisition Level One — isn't programmable, which may prove a strike against the part. The IXP1200 is too expensive for the LAN, Gottlieb said.

But MMC's secret weapon is its switch fabric. All packet processors must hook to a switch fabric, Gottlieb said, and for some time MMC's was the sole merchant switch fabric on the market. Only IBM has produced a similar part, he said.

The CSIX consortium, started by Power X, is working toward a standard interface between the packet processor and switch fabric because most net processor players aren't tackling the latter. Power X will announce its protocol-independent switch fabric at N+I.

But the net processor startups might not be long term players. "If somebody with the size and momentum of Level One can get acquired, I suspect some of these architectures may survive longer than the company name," said Semico's Merritt. The players thus seek to cement OEM deals to validate their respective approaches.

Maker Communications (Framingham, Mass.), last week announced the shipment of its hybrid cell and packet processor, the MXT4400, to such key customers as Cabletron Systems Inc., Lucent Technologies Inc. and Alcatel/Xylan. And C-Port (North Andover, Mass.) is expected to make software partner announcements at N+I.

Agere's Route Switch Processor is optimized for handling up to 65,535 packet queues, allowing ATM-like quality-of-service designations. Agere offers its own FPL high-level language and can give customers access to function calls through C microcode. In some cases, customers may wish to program the processor using their own language.

FPL can interface to Verilog or VHDL simulators and is said to ease programming of such functions as describing and modifying header fields, creating subnets and optimizing for table-lookup strategies.

Hyperchip, for its part, has chosen the ARC Cores Ltd. 32-bit core generator architecture to create a HyperMatrix chip with 32 cores configured as "transmitters" in a crosspoint matrix. Hyperchip has recently focused on using the HyperMatrix design to develop its own petarouters, which chief technology officer Richard Norman calls the next step for backbone services beyond terarouters.

Hyperchip is developing a design for a line card with 5-Gbit/second capabilities for carrying quad Gigabit Ethernet or single OC-48 services. The line card would use an I/O-intensive network processor for which ARC Cores is one of several contenders under consideration.

Speed secrets

In the Hyperchip design, most first-pass traffic shaping and quality-of-service assignment would be performed by the line-card processor. By the time packets are assigned to the HyperMatrix, only very simple packet forwarding decisions need be made at each ARC node. That lets the chip achieve speeds unprecedented in router architectures, Norman said.

Critics examining pipelined multichannel devices, or pattern engines that reduce packet search-spaces, have questioned whether Hyperchip's degree of on-chip parallelism will prove viable and cost-effective to implement. Norman predicted the company could beat other router architectures to market by the time wave-division multiplexing sends backbone speeds to 40 Gbits/s and above.

The market will take another leap in Atlanta when Solidum Systems Corp. (Scotts Valley, Calif.) rolls its PAX.core 1000, which it calls the first gigabit-classification engine. Since solidum pioneered the Packet Description Language, its offerings could represent a new front in synthesizable cores for packet processing.

— Additional reporting by Robert Ristelhueber