Three pool efforts to build quad SRAM

The part is the next logical step from the zero-bus turnaround (ZBT) SRAMs developed by IDT and the NoBL parts sold by Cypress. In both cases, the SRAMs could switch between read and write states without incurring a wait state in between, thus speeding performance.

That step was critical because networking applications required the parts to flip between read and write states frequently. For SRAMs designed for PC level-2 cache, the need to change states quickly wasn't an issue. SRAMs have had to become more specialized as that level-2 cache has been integrated onto CPUs.

To increase speed further, companies such as Cypress and IDT also developed double-data-rate parts, which could perform read or write actions at both the rising and falling edges of every clock pulse, doubling the clock's throughput.

The QDR parts add speed by putting read and write functions on different ports. This, in addition to a double-data-rate architecture, allows the parts to complete four read or write operations per clock cycle.

That should provide enough muscle for QDR parts to stretch up to 500-MHz speeds, said Mathew Arcoleo, product marketing manager for Cypress. The ZBT and NoBL parts have climbed only as high as 200 MHz.

NoBL and ZBT were similar enough that both camps decided to combine efforts on the QDR SRAM. The QDR architecture was designed from scratch and is based on neither ZBT nor NoBL, Arcoleo said.