IBM, Motorola write Book E on the PowerPC

Book E may give Motorola and IBM a way to present a common front in both the embedded and desktop sectors. It will build a foundation under system-on-a-chip designs that might incorporate intellectual property (IP) cores sourced from commercial IP vendors, or from the core libraries now under construction at both IBM and Motorola.

Over the next year both companies will come out with next-generation PowerPC controllers that adhere to the Book E definition, and will work to ensure that tool vendors create a common software-development environment. The companies also will offer PowerPC licenses to customers and foundries that want a wider number of sources for high-volume designs.

At the Embedded Processor Forum here this week, Tom Sartorius, an IBM Microelectronics engineer, said Book E includes 84 new instructions for 64-bit addressing and other extensions. The Book E architecture is compatible with 32-bit code written for existing PowerPC implementations.

Moreover, Book E defines ways that application-specific processing units (APUs) can be linked to a PowerPC processing core. The AltiVec PowerPC vector processing unit and instructions would be considered an APU under the Book E definition.

Asked whether IBM will develop a PowerPC that includes an AltiVec coprocessor, Elliott Newcombe, PowerPC product marketing manager at IBM's Research Triangle Park facility, said IBM is considering adding an AltiVec APU to one of IBM's designs.

"AltiVec could be an example of one of these coprocessors that could be plugged in [to a Book E-compliant PowerPC]," Newcombe said. "Nothing precludes IBM from doing that, but I cannot comment on whether a design is in progress. The market will decide whether we do that, and I can just say 'stay tuned.' "

IBM and Motorola have been under pressure from its largest customers, largely in the networking portion of the embedded space, to come up with a licensing scheme that would allow them to "choose which foundry the customer wants to go to," Newcombe said. While providing a licensing model, both IBM and Motorola will work to keep those designs on their own process technology and "keep our own fabs full," he said.

Will Swearingen, the PowerPC marketing manager in Motorola's Semiconductor Products Sector, said Book E and the ability to link APUs will fit Motorola's goal of bringing more of its internal IP library to the PowerPC space. Book E, the APU link, as well as the licensing and user-definable op codes, will bring the PowerPC to a new level of flexibility, he said.

"The customer is saying, 'give me more options.' We want to do this to make PowerPC more pervasive," Swearingen said.

Sartorius said Book E will support existing 32-bit applications at the object-code level, as well as "adding 64-bit capabilities in a clean and simple way." The 84 new instructions, out of a total set of about 230 instructions, will enhance 64-bit programming, improve the flexibility of memory management and enhance the interrupt structure. A more-powerful debug framework and timer functions for hard real-time constraints are supported in Book E, Sartorius said.

The Book E specification is available on the Web from either the Motorola or IBM Web sites.

Tom Starnes, the senior analyst for microcomponents and DSPs at Dataquest Inc. (San Jose, Calif.), said that diverging controller designs from Motorola and IBM had made it difficult for tool vendors. Both companies have sought to bring PowerPC designs to networking, but the various PowerPC implementations had different approaches to timers, interrupts and other key functions.

IBM's decision last year to withdraw from the Somerset design center in Austin, Texas furthered the perception that the PowerPC architecture might diverge. To counter that, a Book E development group was set up last year to draw a 64-bit architecture that would provide compatibility with 32-bit designs.