Analysis: Intel broadens base to Web-aware embedded worlds

Analysis: Intel broadens base to Web-aware embedded worlds
NEW YORK — Intel Corp. kicked off its annual analysts' meeting on Thursday (April 22) with a pledge to rapidly reshape itself from the microprocessor behemoth largely linked to desktop computing into a broader-based player with major thrusts in backbone servers, embedded CPUs, communications and networking components, and electronic commerce.

Despite Intel's optimistic picture of a vendor with a cutting-edge view of a millennium that's tilting away from PCs, industry observers noted two big challenges: Amid intense competition, the company must promulgate its advanced StrongARM embedded processors — acquired from Digital Semiconductor — in everything from Web appliances to cellular phones.

At the high end, Intel must begin to move its IA-64 architectures and companion Merced CPU out of the lab and into the marketplace.

In the background, one common but often overlooked software trend that will affect the competitive landscape is the emergence of very long-instruction-word (VLIW) software in all these arenas.

Initially, the biggest challenge could be implementing what amounts to the stealth embedded strategy that's been shaping up at Intel. The company has been reluctant to pull all its embedded efforts under a single umbrella, but it was increasingly clear this week that Intel is looking for design wins in downsized, Internet-aware devices — the same territory Texas Instruments, Motorola and Analog Devices are attempting to plow.

"We're actively pursuing all opportunities here, whether it's with an Intel component or StrongARM," said Craig Barrett, president and chief executive officer of Intel (Santa Clara, Calif.). He added that Intel will release details of its next-generation StrongARM processor early next month.

In terms of delivering high performance at low power, that chip could put Intel in a good position in the new-age embedded market. "Our objective is to move StrongARM into the cellular and Web base," said Paul Otellini, executive vice president and general manager of Intel's Architecture Business Group. "We plan to support a variety of operating systems, include Linux, Be and Wind River's VxWorks." [The latter is a real-time OS.]

Otellini characterized the activity as "nascent" but added that products incorporating StrongARM design wins could be expected by the end of the year.

Intel's relationship with Analog Devices will provide a key source of future StrongARM-based products, industry sources said. The companies are working together at a joint development center in Austin, Texas, to create a merged DSP/CPU architecture. Sources would not specifically confirm that a StrongARM is part of the plan, but they believe it is likely.

On the DSP side, the requirement of consumer-level speech recognition will help define the project. More specifically, the DSP architecture is thought to be an advanced ADI-compatible design, probably 16 bits. The target market is the consumer communicator space, with added features for voice command and, possibly, voice input.

"You could imagine putting a StrongARM processor with some DSP and flash capability as a very interesting driver for a cell phone," said Otellini.

One big reason for the link-up is Intel's desire to play in emerging communications arenas targeted by Motorola and TI, without having to invest too many resources. "Intel doesn't want to be a DSP vendor," said a source. "However, they see a rash of communications-centric equipment coming. There will be a whole new leg of Intel based on signal processing."

Even more crucial for Intel's progress will be the ultimate transitioning of its mainstream microprocessor technology to its new IA-64 architecture. Here, the driving force is the emerging Internet economy.

"Our vision is unwavering," Intel's Barrett said at Thursday's analysts meeting. "We're looking at a world of a billion connected computers with millions of servers in the background and trillions of dollars of electronic commerce."

Presumably, many of those servers will be equipped with Merced, which will be Intel's first implementation of the IA-64. Barrett reiterated that Merced will sample later this year. "Merced is in its final stages of circuit design and layout," he said. "We're looking for samples this year and production volumes in mid-2000. We're equally excited about the follow-on processor, called McKinley, which will sample in late 2000 with production in late 2001."

As for developers, sources report they have not yet seen Merced silicon. For development, they still must work with a "presilicon software environment," or emulator, which Intel has provided in lieu of CPU hardware. However, sources hinted that the emulator has gone through at least one revision since last year and that a full-blown software developer's kit (SDK) is complete.

Though the SDK isn't thought to be widely available, Intel has provided it under tight nondisclosure restrictions to a host of software houses. It will run with a 64-bit-ready version of Windows NT and other 64-bit OSes in the works for Merced, such as an IA-64 release of HP-UX from Hewlett-Packard, Unixware from SCO, Irix from Silicon Graphics, Modesto (a 64-bit version of Netware) from Novell, Solaris from Sun and Unix from Digital.

On the hardware front, one bright note is that Intel is already buzzing out the 0.18-micron process technology that it will use to produce Merced. If all goes well, that could put to rest questions about potential yield problems for Merced.

Barrett noted that Intel will ship its first 0.18-micron chips this quarter. Those will likely be mobile processors. Intel will start cranking out 0.18-micron Pentium IIIs next year. The process will enable the company to field production processors that easily hit 1-GHz clock speeds, he said.

As both embedded and 64-bit efforts move forward at Intel, one issue that lingers over the entire industry is the sea change that's occurring in software. There is a shift away from code written to run on traditional superscalar processors and toward VLIW software, which must be divided up by a compiler into numerous instruction streams that execute on multiple function units within a single chip.

Intel perhaps faces a bigger challenge in that regard than any other company in the industry. The reason is that DSP-only vendors don't have to worry as much about upward instruction-set compatibility as do architects of general-purpose CPUs.

As a result, some experts opine that it's harder to write optimized software for a general-purpose processor like Merced than it is for a DSP. A concomitant reason is that general-purpose chips tend to run large applications (where optimization is often a moot point), while DSPs run more time-constraint apps, such as cell-phone programs.

On the positive side, the upshot is that regardless of whether a vendor is focused on DSPs or general-purpose CPUs, there is a growing body of industry knowledge about how to create VLIW-like code. (Officially, Intel says Merced is not VLIW. It is EPIC — for explicitly parallel instruction computing — which incorporates some VLIW concepts.) Indeed, with a leg in both worlds, Intel may be able to come up the learning curve relatively quickly.

"In fact, there are optimizations you can do to reduce the code in the EPIC world," one compiler expert told EE Times.