Deep-submicron debate flares at Tau-99

Deep-submicron debate flares at Tau-99
MONTEREY, Calif. — Although EDA vendors have already answered the question in the affirmative, an academic debate over whether it's crucial to link synthesis and physical design flared anew at this week's Tau-99, an IEEE workshop on timing issues in digital systems. Controversial research that suggests interconnect delays actually decrease with smaller feature sizes took center stage in a session entitled "How Deep is Deep Submicron."

The research in question surfaced earlier in a paper given by Kurt Keutzer, professor of electrical engineering and computer science at the University of California at Berkeley, and Dennis Sylvester, a graduate student, at the ICCAD conference last fall. The paper stated that interconnect delays for 50,000-gate blocks can be minimized, given new materials and proper drive strengths. At Tau-99, Keutzer argued that chip-level assembly, not linking synthesis with physical design, is the key to deep-submicron design.

Lawrence Pileggi, professor of electrical and computer engineering at Carnegie-Mellon University, agreed that chip-level assembly and inter-block wiring are the most significant challenges. But Pileggi, who also serves as chief technology officer for startup Monterey Design Systems Inc., argued for "placement-aware synthesis" as a way of providing timing closure.

Synopsys Inc. and other EDA vendors stress the importance of linking synthesis with physical design, and Don MacMillen, vice president of the advanced technology group at Synopsys, reflected that view. He said the "small block design style" advocated by Keutzer and Sylvester poses many challenges, and emphasized the importance of timing budgeting, which Keutzer dismissed as the wrong approach.

Keutzer's research has received much attention because it flies in the face of industry presumptions that increasing interconnect delays are the primary problem behind deep-submicron design. But Keutzer's paper's use of analytical models and empirical design data has led even some critics to concede that at the 50,000-gate module level, at least, interconnect delays might not be increasing as was once thought.

The question then becomes how one integrates hundreds, or potentially thousands, of blocks with 50,000 or fewer gates onto a single chip. "The real problem is not designing one of these blocks," Keutzer said in his Tau-99 presentation. "It's how to assemble thousands of these blocks given interconnect and power issues."

Keutzer said that the "real" deep-submicron problems are chip-level assembly, the divergence of local and global clocks, and chip-level clock distribution. The "real" solutions are a modular, hierarchical design strategy based on 50,000-gate or smaller blocks; a disciplined routing hierarchy; avoidance of scaled global wires; and flip-chip packaging.

Linking synthesis and physical design, Keutzer said, can help close the speed, area and power gap between automated and manual design approaches. "It can be useful, but just don't try to pass it off as a deep-submicron problem," he said.

Pileggi gave some support to Keutzer's view. "The real problem is going to be the assembly of the blocks themselves," he said. "Global wires are the problem we have to worry about — they don't scale with next-generation designs."

As feature sizes shrink, he noted, the global or inter-block wires increase in absolute number, and the global wirelength increases relative to local wirelength. And not all the global wires can be routed as the designer might want.

Pileggi said, however, that the Keutzer/Sylvester paper presumes an "ASIC viewpoint" with respect to the wireload ratios of the blocks. Results might be quite different, he warned, for full-custom design, or even for future ASIC cell libraries.

Physical location will be important for all blocks, Pileggi said, and therefore placement-aware synthesis is needed to help address the timing closure problem. He said it will also be important to re-map or re-synthesize logic during physical design.

MacMillen noted that current synthesis tools use average-case net capacitance to model wire loads, even though designers need to minimize worst case path delay. Today's wire-load estimates do not model capacitance distribution, he said, leading to over-constrained nets that result in larger gates, or unmodeled long nets that cause critical-path violations.

To some extent, he acknowledged, smaller blocks provide better convergence between preplacement and post-routing timing estimates. But MacMillen said the small block design style results in a lot of manual decision-making for such criteria as aspect ratios, placement, and pin locations. Also, he said, time budgeting becomes much more difficult for designs with many small blocks.

"I think we need to merge physical design and synthesis today, to solve today's problems," he said. "The goal is to move us to larger block sizes."

During a question-and-answer period, Keutzer disputed the usefulness of timing budgeting, which is used to allocate relative timing budgets to components and interconnects. "Timing budgeting is not the way to go," he said. "We need an optimization framework for chip-level interconnect as well as extra-module gate delay."

Tau-99 is an annual ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems. This year's conference examined such topics as static timing analysis, asynchronous design, timing issues in silicon-on-insulator, false paths, and interconnect analysis and optimization.