Synopsys unveils 'plan' to reinvent IC design

Synopsys unveils ??plan' to reinvent IC design
MOUNTAIN, VIEW, Calif. — Claiming a methodology shift comparable to the emergence of synthesis, Synopsys Inc. last week rolled out its long-awaited design-planning software. By combining synthesis with full placement and global routing, Chip Architect places Synopsys directly in the IC-layout market and promises the first real union between synthesis and physical design.

Design planning-a combination of register-transfer level (RTL) floor planning, fast synthesis, global routing, and timing and power estimation-has been the missing link in the system-on-a-chip design methodology. Because design planning is viewed as crucial for million-gate, deep-submicron chips, Synopsys is engaged in a race with Cadence Design Systems Inc. and Avant! Corp. over who will field the first successful solution.

"We truly believe we are coming to market with a next-generation design flow," said Synopsys chief executive officer Aart de Geus. "We are focused on the new generation of system-on-chip design, and this is the foundation of that new age."

Chip Architect works at the black-box, RTL and gate levels. It includes floor planning; placement; global routing; and timing, area and power estimation, all linked together with the PrimeTime static timing analysis engine. Synopsys calls the approach physical synthesis.

But the company faces tough competition from Avant! Corp. (Fremont, Calif), whose Planet-RTL product offers many of the same capabilities. And Cadence Design Systems (San Jose, Calif.), which has yet to field a successful RTL floor planner despite an initial 1995 introduction, is gearing up to provide its own vision of design planning.

Moreover, several startups have moved into the design-planning area in the past year, including Aristo Technology (Cupertino, Calif.) and Tera Systems (Campbell, Calif.). Recently, Sapphire Design Automation (Santa Clara, Calif.) offered software that could fall into the category, and Iota Technology (San Jose) is preparing an estimation tool called RealPower.

The activity is all based on the realization that synthesis and layout must become closely intertwined. But will the resulting design flow be layout- or synthesis-centric? Synopsys' fortunes depend on the latter. Cadence and Avant! will hold out for the former, maintaining that design-planning tools must come from the same vendor that provides cell-level place-and-route.

The RTL prototype

Design planning is the enabler for the RTL "virtual prototype," which Dataquest Inc.'s principal EDA analyst, Gary Smith, has identified as the most important development in EDA. Smith said the RTL virtual prototype consists of four components: an RTL floor planner, fast global router, fast synthesis engine and concurrent analysis capability for timing, power, signal integrity and electromigration.

With the exception of signal integrity and electromigration, Synopsys now claims to have all those capabilities. The company also claims to have done groundbreaking work in IC placement, resulting in shorter wire lengths and improved routability. At $250,000 for the fully loaded version, Chip Architect is priced to compete with place-and-route tools from Cadence and Avant!, and it's said to handle everything up to but not including cell-level routing.

The Chip Architect announcement was made with endorsements by Toshiba, STMicroelectronics, Panasonic and Siemens, all of which served as development partners. Tomohisa Shigematsu, senior vice president at Toshiba America Electronic Components, said Toshiba used the tool on three actual designs, ranging from 170,000 gates to 1 million gates. He said the tool showed delay controllability within 5 percent of the design specification.

Similarly, Marco Casale-Rossi, design-automation partnerships manager at STMicroelectronics, said that on a block of 350,000 gates, Chip Architect had 7 percent less wire length and half as many routing violations. It required 2.5 hours, vs. 4.25 hours of routing time via the traditional Synopsys-to-Cadence place-and-route flow.

Keith Hirayama, vice president of Panasonic Semiconductor Development Co., said the company used the tool successfully in designing a 0.35-micron mobile-communications chip and a 0.25-micron DVC chip.

When asked whether they would renegotiate their contracts with Cadence and Avant! because they now use Synopsys placement, the semiconductor partners said they will support their current place-and-route (P&R) flows but are preparing internal groups to ramp up on use of the new tool.

John Cooley, moderator of the E-Mail Synopsys User's Group (ESNUG), said the technology announcement should give Cadence and Avant! executives nightmares. "This is a big deal," he said. "Synopsys is moving into their territory with an eclipsing technology.

"User benchmarks are telling me that Chip Architect is giving estimates on the RT level that are within 5 to 10 percent of the final silicon," Cooley said. "If true, this is incredibly useful because I'm otherwise stuck using ridiculously conservative front-annotated wire models or doing 20 iterations with my good buddy the P&R guy."

Synopsys' de Geus said that three basic approaches will address the timing-closure problem: bottom-up, "Super Glue" and top-down. Bottom-up tools will add bits and pieces of synthesis into place-and-route. Super Glue tools will come from startups but will be ineffective because they do not have either of the key tools (synthesis and place-and-route).

Synopsys represents the top-down approach, de Geus said.

He argued that the Chip Architect announcement carries a "similar magnitude" to the announcement of Synopsys' first synthesis tools. "Synthesis connected RTL to gates, and that was a quantum leap," he said. "This now connects RTL all the way down to detailed placement and a certain amount of routing. If we execute on what we're saying, it will have a huge impact on the design flow in the future."

Chip Architect has been in development for several years. A Synopsys contract with Sematech helped outline the initial vision of the product, and Synopsys' acquisition of IBM technology helped build the floor-planning portion. But the detailed placement was designed within Synopsys, de Geus said.

Synopsys' recent purchase of Everest Design Automation will apparently figure into Chip Architect in the future. For now, the product has a global router that Synopsys developed internally. Down the road, it's likely to include the top-level router that Everest has developed. While global routers are for estimation purposes, top-level routers provide more complete work.

Chip Architect is first used at the black-box level, where some portions of the chip may be undefined and others could be hard macros. "Here, the design team is trying to determine the right floor plan to meet the performance objectives of the chip," said Sanjiv Kaul, general manager of physical synthesis at Synopsys. "You might do pin assignments, connect long nets that are top-level routes between blocks, and start timing analysis with PrimeTime."

The goal at the black-box stage is time-budgeting, which defines how much time is allowed for various signals, and power planning, which gives a first estimate of how much power blocks are consuming and how power requirements will affect routing.

Chip Architect is then used at the register-transfer level, after RTL code is written but not necessarily verified. Here, users run a quick synthesis, do placement and get timing, area and power estimates that Synopsys claims will be accurate to within 25 to 30 percent. Chip Architect itself runs the quick synthesis.

Kaul said that both synthesis and cell-level placement are essential to get accurate estimates. While Chip Architect offers a cell-level placement in the RTL phase, it's not a "legal" placement in terms of design rules; such a placement would take far longer. Chip Architect also offers clock-tree synthesis during the RTL phase.

In addition to placement, the output of the RTL phase includes timing and power budgets for synthesis, a detailed floor plan, timing estimates, custom wire-load models and a congestion map for routability.

The final phase of usage is at the gate level, where Chip Architect generates a detailed, legal placement that can be passed to Cadence or Avant! tools through industry-standard formats. The final phase also offers global routing and in-place optimization, which lets users resize buffers.

Chip Architect is available now and initially supports 14 ASIC libraries, with more slated soon, Kaul said. The product assumes the use of Synopsys' Design Compiler.

Planned competition

The strongest initial competitor to Chip Architect appears to be Avant!'s Planet-RTL, which Dataquest's Smith believes is the best RTL floor planner to date. Planet-RTL includes fast synthesis, global routing and timing estimation, and it generates constraints, scripts, time budgets and wire-load models for Synopsys' Design Compiler.

Avant!'s acquisition of Aceo helped it add synthesis algorithms to Planet-RTL, and that was a major improvement, said Phil George, Avant!'s head of product development. "Synthesis is running because we found the language-inference model is very inaccurate in predicting area and delay," he said.

Avant! now claims area estimates within 15 to 20 percent of final place-and-route and timing estimates to within 5 to 10 percent.

Avant! synthesis, of course, is not Synopsys synthesis, which is used by the vast majority of chip designers. But Avant! emphasizes a common database that links RTL design planning all the way through cell-level placement and routing. Planet-RTL contains many of the same place-and-route algorithms as Avant!'s Apollo placement-and-routing tool, George said.

"The Synopsys solution, as we understand it, does not go the full distance," said Michael Jackson, head of product management for Avant!. "It stops at the global routing phase, and we believe that's a real issue. We believe we're in the best position to understand physical issues."

ESNUG's Cooley said that he has been unable to find any users of Planet-RTL. An Avant! spokesman said that "a number of ASIC houses" plan to integrate Planet-RTL into their design flows, but he declined to provide specific names.

Cadence has had a rocky road in design planning, having introduced and shelved two RTL floor planners: SiliconQuest and Top-Down Design Planner. Steve Glaser, vice president of strategic marketing at Cadence, said some customers are using Cadence's gate-level floor-planning tools along with fast global routing and synthesis, yielding what is essentially RTL design planning. But Glaser could not say when Cadence might offer a packaged RTL floor planner.

Andy McNelly, senior director for solutions development, said Cadence is dividing the system-on-a-chip design flow into three parts. First comes "robust chip planning," which includes RTL floor planning, top-level and global routing, estimation, and time budgeting. Next comes synthesis — presumably through tools Cadence acquired when it bought Ambit last year — and placement optimization. Deep-submicron analysis, optimization and final routing follow.

Ambit engineering vice president Rich Brashears also views Chip Architect as an incomplete solution. Dividing placement and routing between two tool sets, he said, will "introduce differences and unpredictability into the process."

Cadence has a partnership with NEC and is forming a marketing team for RTL design planning, according to sources close to Cadence. The sources said NEC is taking a lead role in testing the solution and is providing feedback for area estimation and timing budgets.

A Cadence spokeswoman would not confirm an NEC partnership but said development activities are under way in "chip planning."

Startups to the rescue

In 1998, when expected design-planning announcements from the major vendors failed to materialize, several startups entered the fray. One is Tera Systems, whose TeraForm product includes floor planning, partitioning and delay estimation. The company claims its solution's ability to partition data path, memory and control creates a "structured ASIC" design methodology.

Tera marketing vice president Richard Gordon said the tool is in use by LSI Logic and others and that it is essentially available now. The product is claimed to include a new form of fast synthesis that compiles to "RTL components" rather than gates.

Aristo Technology is about to beta test a tool that will offer "block-level" topology planning. The tool will create timing-correct, routable design representations, said marketing director Rod Dudzinski.

Newcomer Sapphire Design Automation has a tool that sits between synthesis and layout and provides placement, optimization and analysis. Chip Architect "is an attempt by Synopsys to cover capabilities already available in physical design tools in the market today," said Shashank Goel, president and chief executive of Sapphire. "The functionality to solve the timing closure problem — an appropriate electrical abstraction of deep-submicron effects — is apparently absent."

Design-services house Iota Technologies is readying RealPower, which offers power estimates after synthesis rather than after layout. The tool also analyzes electromigration, IR drop and "hot spots," and assists with power-mesh creation.

RealPower is sold through CyberTech International (Los Gatos, Calif.).

-Additional reporting by Michael Santarini and Anthony Cataldo.