MIPS veterans eye configurable CPU

SANTA CLARA, Calif. — A startup with some impressive alumni from companies including MIPS and Synopsys will announce on Monday (2/15) what is a configurable processor architecture and tools kit for specialized applications.

Tensilica Inc. has leveraged concepts from RISC and VLIW to come up with Xtensa, a 32-bit, low-power instruction set targeting mobile applications, up to 250MHz performance and quarter-micron CMOS.

CEO Chris Rowen, who worked on the originaly MIPS RISC instruction set at Stanford, said the core takes up to just 25,000 gates of logic to implement and can be implemented in fewer than eight hours. Tensilica's offerings also include a development kit based on industry-standard GNU tools, including a compiler, linker and debugger.

Licensing fees for the processor and tools start at $350,000 and the company also charges royalties based upon units manufactured.

The company has lured several notables from the semiconductor and EDA worlds including former Synopsys Chairman Harvey Jones (Chairman), Intel veteran Beatrice Fu (vice president of engineering) and MIPS and SGI veteran and multiple patent holder Earl Killian (chief architect).