Motorola spins PowerPC line for comm, embedded apps

AUSTIN, Texas — Motorola Inc.'s networking systems division has used a special PowerPC 603e core to develop a new family of microprocessors aimed at communications and general-purpose embedded-computing applications.

The MPC8240 includes a full floating-point unit, unlike the MPC8260 PowerQuicc II, introduced in September, which used a 603e core with disabled FPU. The new processor also packs an advanced memory controller with dual-channel DMA, as well as a PCI interface.

"This design began with a clean sheet of paper at Somerset," the PowerPC design center, said Will Swearingen, strategic marketing manager for the networking group. "We anticipate the 8240 family is going to be used in applications requiring a full-featured centralized processor." PowerQuicc and PowerQuicc II, by contrast, are used in local communication-coprocessing applications demanding more performance than the previous 68302 and 68360 generations of communication controller can provide.

As evidence of its wide range of applicability, initial customers for the 8240 include Nortel Networks' Aptis Communications group, the Clariion advanced storage group at Data General, CS Telecom, DY 4 Systems and Motorola Computer Group.

Raj Handa, product line manager for the PowerPC families, said the 8240 will tend to be used by those needing the highest performance in the core processor, at speeds eventually up to 300 MHz (200- and 266-MHz versions are offered initially). The processor can support 66-MHz PCI bus speeds, and the memory controller can support synchronous DRAM to speeds of approximately 100 MHz.

With integrated FPU, the new device raises the question of whether Motorola also might integrate its vector-oriented AltiVec instruction set, or DSP blocks growing out of its StarCore joint effort with Lucent Microelectronics, in a PowerPC core. Swearingen would say only that the 8240 will give rise to a family based on the 603e, and that Motorola is exploring with customers the subject of how many floating-point, vector and general DSP applications should be supported for various applications.

Several features from the 603e core design have been adopted for the 8240, including a 16-kbyte instruction cache, 16-kbyte data cache and special cache-locking features. A programmable interrupt controller on-chip supports multiple timers and counters, and a special messaging unit supports the Intelligent I/O message-passing structure.

Motorola will be sampling the device next month in a 352-lead thin ball-grid array, with production set for next April. The 200-MHz version is listed at $60 in quantities of 10,000, while the 266-MHz version will sell for $90 in similar quantities.