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New Book “Advanced Verification Topics” published by Cadence
Brian Bailey
1/17/2012 11:08 AM EST
I am pleased to see the continued trend of the major EDA companies publishing books on various topics within the industry and doing it in a way that it not tied to their tools (at least I presume this one is not tool related). A couple of years ago, I led a panel session at DVCon and the conclusion of that panel was that education is one of the biggest impediments to the advancement of EDA tools, and books are a great way to attempt to bridge that gap and I believe are a great way for them to be spending part of their marketing dollars.
Today, I learn of a new book penned by Cadence titled “Advanced Verification Topics” which they claim describes in great detail the latest techniques and methodologies for verifying today's most complex IP and systems on chips (SoCs). Penned by eight Cadence verification experts, "Advanced Verification Topics" builds on the prior Cadence® book, "A Practical Guide to Adopting the Universal Verification Methodology (UVM)." The new book delves into such topics as metric-driven verification of digital and mixed-signal designs, low-power verification using the UVM, multi-language UVM, and acceleration for the UVM.
At the moment I can find no other information about the book. No table of contents or anything to help flesh out a review of this book. I have requested a copy from them and in addition asked if they would present a chapter of the book here on the EDA Designline. Hopefully I will be able to bring you a lot more about this in the future.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Today, I learn of a new book penned by Cadence titled “Advanced Verification Topics” which they claim describes in great detail the latest techniques and methodologies for verifying today's most complex IP and systems on chips (SoCs). Penned by eight Cadence verification experts, "Advanced Verification Topics" builds on the prior Cadence® book, "A Practical Guide to Adopting the Universal Verification Methodology (UVM)." The new book delves into such topics as metric-driven verification of digital and mixed-signal designs, low-power verification using the UVM, multi-language UVM, and acceleration for the UVM.
At the moment I can find no other information about the book. No table of contents or anything to help flesh out a review of this book. I have requested a copy from them and in addition asked if they would present a chapter of the book here on the EDA Designline. Hopefully I will be able to bring you a lot more about this in the future.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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