TI's multicore SoC: Right notes, ringing hollow

2/17/2010 6:58 PM EST

For sure, the requirements of next-generation basestations will push all architectures to their limits and beyond. Balancing lower power and lower cost with increasingly parallel, math-intensive processing to meet multiuser demands for high-data-rate data in 3GPP Long Term Evolution (LTE) Release 8 all-IP networks is not going to be easy, especially with the introduction of MIMO, beam forming, OFDMA and many other enhancements engineered to maximize spectral efficiency.

These issues were all at the front of Kathy Brown's mind when she gave me an overview of the new TI architecture. Kathy is manager of TI's wireless basestation infrastructure division and was refreshingly quick to get to the point.

Beyond the impressive basics, such as four-core and eight-core options to start, 1.2-GHz operation and 256 GMACS and 128 GFLOPS performance (eight cores), the use of a 40-nm TSMC process and the incorporation of coprocessors for Layer 1, 2, and 3 processing functions, there are four main architectural innovations being outlined here, each of which are groundbreaking for TI.

Along with mixing fixed-point and floating point, TI's multicore SoC architecture has impressive intentions, such as advanced memory management and a Multicore Navigator to provide core 'load balancing'. Implementation details will be worth waiting for.

The first is the integration of fixed and floating-point processing within each DSP core. The cores are based on TI's 'C64x+ high-performance fixed-point line. Fixed point comes up short with regard to precision when it comes to solving the matrix inversion math required for the likes of MIMO processing, so the combination of both fixed and floating-point processing, if done right, enhances processing efficiency and simplifies programming.

The second feature is the Multicore Navigator. According to Brown, this performs 'load balancing' similar to Apple's Grand Central Dispatch and is a codification of much if what TI has learned about multicore processing. It coordinates data movement throughout the processor and breaks up a task between peripherals and accelerators--without sucking core cycles.

The third is the Multicore Shared Memory Controller. Using prefetch mechanisms the controller 'anticipates' what each core may need and goes, "a step beyond DMA," said Brown. In effect, shared memory becomes as efficient as dedicated local memory.

Last but not least comes the TeraNet 2 2-terabit/s non-blocking on-chip switch fabric that connects all the elements, allowing them all to run simultaneously and independently.

Other features abound, but these are the heart of the new SoC architecture. The problem is that TI is unable to comment about how each of these functions is implemented and how they work. Also, while L1, L2 and L3 processing is supported, only software for L1 is available from TI. It is relying on the TI ecosystem for the L2 and L3 stacks. Furthermore, no concrete data on availability or estimated pricing is anywhere near forthcoming, beyond a timeline 'sometime in the second half of 2010'.

Granted, it's an 'architecture' announcement and not a 'product' announcement, but the lack of detail on the implementation, beyond a sketchy overview that's more akin to a statement of 'intent' vs. actual design, smacks of a rush to market to meet the Mobile World Congress deadline. This contrasts sharply with Freescale's six-core MSC8155 DSP, also for basestations.

This processor also plays host to an accelerator platform technology, in this case MAPLE-B2L, and uses the Gen 2 Serial RapidIO interconnect for inter-core communication. The chip is based on the SC3850 StarCore DSP, which earned the best ever BDTImark2000 fixed-point benchmark.

That I used the term 'chip' is important. Freescale has qualified the MSC8156 in a 45-nm technology and expects to sample to customers in Q3, in a 783-pin FC-PBGA package. I don't expect to see a chip based on TI's new architecture this year. Do you?

By the time it does materialize, will it then seem so far ahead, given what's sure to emerge between now and early 2011 from the likes of Freescale, as well as core vendors such as CEVA and heterogeneous processing vendors such as Altera and Xilinx, both of which are moving way beyond formal interpretations of FPGA and do already have relationships with basestation vendors. It'll be an interesting year. What do you think?

For more on the new SoC and how to take advantage of it, read:
Realizing Full Multicore Entitlement and Enabling LTE Development with TI's New Multicore SoC Architecture