FPGAs at 40 nm and >10 Gbps: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers

This paper describes key technologies that enable Stratix IV GT FPGAs to deliver the performance and capabilities necessary to support 40G/100G applications with integrated 11.3-Gbps transceivers. These include the LC-based oscillator and decision-feedback equalization (DFE) at 40 nm for ultra-low jitter FPGA transceivers. Furthermore, the transceiver architecture, including clocking and clock data recovery (CDR) technologies, are highlighted, as well as performance validation results.