Design Patterns for Packet Processing Applications on Multi-core Intel Architecture Processors

This paper describes several key design aspects for consideration when implementing packet processing applications on multi-core Intel architecture processors, presenting the inherent design problems and exploring solutions for each.

This paper also aims to help the developers seeking a methodology for how to optimally use the powerful Intel multi-core processors for packet processing when making the transition from NPUs or ASICs to multicore Intel architecture processors or when developing new applications