A Low-Cost Single-Event Latchup Mitigation Scheme

Adjacent n-type and p-type regions in CMOS circuits may form a parasitic thyristor composed of two pairs of parasitic bipolar transistors. A spurious current spike in one of these transistors may be amplified by the large positive feedback of the thyristor and cause a virtual short between Vdd and ground, resulting in a latchup. A single-event latchup (SEL) occurs when the spurious spike is induced by an ionizing particle.

Single-event latchup (SEL) is one of the most threatening single event occurrences possible, as the induced current may destroy the affected device. Existing latchup mitigation schemes may induce a very high area cost or may require modifying the fabrication process. In this paper, a new single-event latchup mitigation approach is presented, to be implemented at the design level. The technique protects devices from destruction and preserves circuit state at very low area cost.