Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog

Verification is one of the biggest challenges for SoC designs, and traditional methods have run out of steam. To address the verification challenges of today's large and complex chips, design teams are turning to advanced and unified verification methodologies that leverage multiple technologies. This paper shows how to start performing constrained random verification quickly by applying just five vital steps using DesignWare Verification IP and Synopsys' Reference Verification Methodology (RVM). All concepts and techniques can be used in testbenches based on the Verification Methodology Manual (VMM) for SystemVerilog. This is a subsequent paper that builds on this one: "Advanced Techniques for Robust Testbench Development with DesignWare(r)Verification IP and Verification Methodology Manual (VMM) for SystemVerilog"