Design specific variation in pattern transfer by via/contact etch process: full-chip analysis

We have developed a novel model-based full-chip algorithm providing a capability to control the design specific variation in pattern transfer caused by via/contact etch processes (VCE). This physics based algorithm is capable to detect and report etch hotspots based on the fab defined thresholds of acceptable variations in a prospective dry etch process step. Physical model for the etch rate of an arbitrary feature, incorporated into the developed algorithm, takes into account both the phenomena: an across-die variation in neutral species fluxes caused by global pattern density variation (microloading) and aspect ratio-induced variation in intra-feature radical transport resistance. All the information about the die layout is implicit in the solution, so there is no need for the analyzed etch step to be run on a specially designed test chip. VCE model/algorithm was successfully validated and calibrated on real silicon for a variety of etch steps employed by Toshiba manufacturing.