Thermal Transient Characterization of Single and Stacked-Die

This paper proposes an unambiguous definition for the junction-to-case thermal resistance, based on a transient measurement technique with much higher repeatability for very low thermal resistances compared to existing two-point measurement methods. The technique is illustrated on thermal transient measurements of power MOSFETs. The concept is extended to multi-chip and stacked-chip structures, where transfer impedances have to be introduced.