Tech Papers
A Tutorial on using Precision Synthesis for Lattice Devices
Mentor Graphics, Lattice Semiconductor
Mentor Graphics Technical Library
February 2006
This paper demonstrates how to use Mentor Graphics Precision Synthesis tool with Lattice ispLEVER software to synthesize a Verilog HDL design and generate an EDIF file for a Lattice MachXO device. A similar flow may be used for LatticeEC/ECP and LatticeXP designs.
Note: By clicking on the above link, this paper will be emailed to your TechOnLine log-in address by Mentor Graphics.
Rate this Content
|
|
|
|
|
Navigate to related information
