Tech Papers
Using Strong Types in Your SystemVerilog Design and Verification
Mentor Graphics
Mentor Graphics Technical Library
June 2007
SystemVerilog introduces strong types on top of the existing weaker Verilog data type system that can provide an environment similar to VHDL. SystemVerilog also introduces many new types used by the software developer that are useful for verification. This paper introduces methodologies for taking advantage of SystemVerilog's type system for both the designer and verification engineer.
Note: By clicking on the above link, this paper will be emailed to your TechOnline log-in address by Mentor Graphics.
Rate this Content
|
|
|
|
|
Navigate to related information
