Addressing Reliability and Circuit Verification Challenges with Calibre PERC

Circuit design implementation has become progressively complex in deep submicron technologies. Multiple processor cores, I/Os, several types of memories, complex analog circuits, and synthesized logic are being designed onto the same chip. Advanced IP integration proficiency strategies are needed to realize today's complex systems-on-chip (SoC) designs, not to mention the high demand in the communications semiconductor market. Ensuring product reliability to meeting all design goals while achieving good yield is a significant and growing challenge. Today, designers need physical verification tools with greater flexibility and the power to handle emerging circuit verification demands, such as the ability to deal with more complex design rules, multiple voltage domains, and advanced device parameters.