Implementing DDR3 DIMMs with Modern FPGAs

This paper looks at how high-end field programmable gate array (FPGA) I/O cells interface to DDR3 SDRAM to take advantage of its speed and power benefits. It examines how leveling is achieved in the FPGA for operation with a DDR3 SDRAM DIMM memory; the benefits of using dynamic on-chip termination (OCT) to match the impedance on a bidirectional bus and save power; and the advantages of using variable I/O delay for deskew within a DQS group. It also discusses the importance of simulating with tools such as Mentor Graphics HyperLynx to ensure the best eye quality.