Tech Papers
Reducing IC Cycle Time with Calibre
Mentor Graphics
Mathew HoganMentor Graphics Technical Library
August 2008
The same shrinking of transistor size that has enabled chip designers to place significantly more functionality on the same die area is responsible for substantial increases in the number and complexity of verification rules. This paper describes a solution: the Calibre suite of verification tools, specifically Calibre nmDRC, Calibre nmLVS and Calibre Incremental DRC.
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