Configurable, Programmable Reed Solomon Decoder

A new Reed Solomon (RS) decoder architecture that can process multiple symbols per clock cycle is described. The number of bytes processed in one clock cycle, along with other variables defining the RS code, are implemented as generics in the VHDL design to provide the user a choice between the optimization of system area and system speed. These generics give system designers the ability to quickly make tradeoffs, without re-designing the decoder.