System-Level Design in the SoC Era

Though a lot of attention is being given to the deep submicron technology that enables the system-on-chip (SoC) era, the bigger picture of the system-level design flow is seldom systematically addressed. This paper provides an overview of the limitations of current systemlevel design flows within the context of a generic flow. A system-level infrastructure to support the modeling of hardware, software and systems and enable co-design will be proposed.