Improving Computational Efficiency While Reducing Power Consumption in Newer Microcontroller Generations

The best way to simultaneously meet high performance, low power, and low system cost is to combine state-of-the-art, low-power semiconductor processes with power management techniques, improved architectures, and co-processors. Since cost reduction dictates smaller die sizes, performance and power dissipation must be scaled on newer microcontroller product generations to realize a net improvement factor. Along with the ARM926EJ CPU with embedded DSP instructions and the Java accelerator, a floating-point co-processor and a switched bus fabric is used to provide a much improved MIPS/milliwatt figure of merit using a 90 nanometer process optimized for low power. Power optimization is accomplished through process and technology development, and architectural means.