DS33R11 Multichip-Module BSDL Testing

This application note describes how to alter the printed wiring board (PWB) netlist of a design containing the DS33R11T1/E1/J1 transceiver so that the netlist complies with the Joint Test Action Group (JTAG) specifications. These alterations are necessary because the DS33R11 was designed as a multichip module with multiple die in a single package which cannot be defined by the Boundary-Scan Description Language (BSDL) for board-level JTAG testing. The application note contains external pin mapping tables, internal die-pad bond tables, and contact information, in order that the designer can quickly achieve accurate JTAG boundary-scan board testing.