Simultaneous Power-Down Sequencing with Linear Regulators

The most recent DSPs and FPGAs have more relaxed requirements for core and I/O power-up/-down. However, a few still specify power-up ramp rates and recommend sequential sequencing for predictable and repeatable start-up. Even fewer specify power-down requirements, including ramp rates and/or sequences. Therefore, the ideal method for DSP and FPGA power up/down is for all rails to rise and and fall at the same time and rate.

This article explains how the TPS74x01 family of linear regulators provides simultaneous power-up sequencing and, with the assistance of simple pull-down circuitry and/or careful sizing of the load resistance at power down, two different methods for achieving simultaneous power-down sequencing.