Break Points
Intel's Ambitious Process Roadmap
Jack Ganssle
9/20/2009 7:00 PM EDT
One might be skeptical. Except twenty years ago we wouldn't have believed the industry would have achieved 45 nm, which is so much shorter than a wavelength of light that pundits were predicting the end of Moore's Law.
And in 2004 Intel was predicting much the same (see Slide Three in its IDEM presentation..) Over the last five years they have been amazingly accurate in forecasting process scaling.
The company thinks they can continue to scale with current sorts of technologies, but admit to hoping for a bit of magic, er, "another technological breakthrough," to get to 8 nm. That's nearly a decade away, though, and a lot can happen in ten years.
Some of their current parts sport over 800 million transistors. Toss that number into the Moore's Law cauldron and high-end parts might have 100 billion transistors in 2022!
What will we do with all of those? Multi-core runs out of steam, unless one goes to unique architectures that don't work well with general purpose computing, at around 8 cores. Perhaps they'll be building many-core-friendly specialty parts like GPUs. Or will caches explode in size?
And what will a fab cost?
Another site that covers this story has a funny comment from a reader: "maybe after 2024 Intel might round up the value [process geometry] to zero and stop processor manufacturing.
Since inventing the microprocessor nearly 40 years ago, Intel has been the leader in both microprocessors and process scaling. Clearly this industry has many exciting developments ahead. I wonder what killer apps will make use of 4 nm parts?
(Editor's Note: Jack's Embedded Poll Question this week is " What will we see in 2022?" To vote go to the Embedded.com Home Page.
Jack G. Ganssle is a lecturer and consultant on embedded development issues. He conducts seminars on embedded systems and helps companies with their embedded challenges. Contact him at jack@ganssle.com. His website is www.ganssle.com.
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Les Slater
9/21/2009 12:03 PM EDT
Long before 2022 will have automatic conversion of 2d to 3d movies along with greatly enhanced recovery of potential resolution and great reduction of noise.
With sufficient multiple camera source locations we will be able to generate multiple, but different, arbitrary source locations in real time.
We will be able to produce movies from models of actors and their environment synthesized totally from script.
The above examples are mechanical and greatly deterministic in nature but we can expect great enhancements in reasoning and association being accomplished as hardware and software become much more advanced.
Multiple cores will reach practical limit in most applications and things like GPUs will be integrated but more importantly more and varied resource blocks will be available on die.
It will become much more apparent that the distinction between hardware and software will greatly diminish.
Most importantly, formalities will have to developed to map problem, task space into resources available.
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krwada
9/21/2009 6:26 PM EDT
I wonder what the 3d Internet will be like??? Maybe I should not entertain the thought eh?
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chipmnk24
9/22/2009 10:47 AM EDT
I sit here with an programming project containing a CPU and an FPGA right next to it. (I am blessed :-))
The FPGA will scale all the way to the 100 billion transistors (if Altera or Xilinx match Intel's scaling). It will scale smoothly and there will be no forced paradigm shift. There WILL be new ideas and opportunities and optional alternative paradigms but compared to the CPU road-maps the FPGA ride will be one smooth glide.
As exciting as those new multicore chips are, the "jolt" when new models arrive to replace older ones is even more pain. (Or somebody elses business...)
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Les Slater
9/23/2009 12:10 PM EDT
re -chipmnk
And of course we've had CPU resources, both soft and hard, as part of FPGAs for some time now. I agree FPGAs should scale similarly in same time frame.
I see the CPU religious wars receding in the future. In the Intel high end architecture roadmaps we see an attempt to do everything. The limits to this will become apparent relatively soon. It would seem more reasonable to embed relatively simple CPU resources in a sea of other resources such as abundant FPGA, memory, data and control routing, math, FIR, whatever. The particular mix would be determined by what kinds of problems were being addressed.
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chipmnk24
9/23/2009 12:50 PM EDT
Re- Les Slater seeing CPU religious wars receding in the future....
Now, that I don't see. It is extremely difficult to root them out of our embedded-electronics-ecology. They are everywhere from the field to oouter-space, from college training courses to your desk. AND there will probably always be CPUs and ASICs that can beat an FPGA in one corner or another.
However it is interesting to speculate. Are those programmers who've started delivering software on the latest CELL processor now looking forward to the next? (Answers to this thread would be interesting.)
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Les Slater
9/23/2009 1:47 PM EDT
The RISC/SISC wars have all but died; similarly so will current CPU religious wars. Legacies from the field to outer space are just that, legacies. We are not bound by those legacies or any religious feathers they may have raised. We move on.
A CPU or ASIC beating an FPGA in one corner or another is not particularly interesting. I am suggesting a mixture of varying technologies and resources. No need to rule out ASIC, whatever that might mean in the 10^11 transistor die.
Your pointing to the CELL processor is more interesting. This is an early example of the direction Im pointing to. You also point to its difficulties. That is why I ended my first post here with: Most importantly, formalities will have to [be] developed to map problem, task space into resources available.
A very sophisticated compiler, mapping to a particular assemblage of resources might be considered a primitive case of what I am suggesting. More generally I am suggesting a new formality, a geometry maybe, mapping problem and task space to target assemblage of resources, or maybe a library of resources. The problem or task space would include but not be limited to restraints, dependencies etc. This is a very difficult, but I think necessary, undertaking if we are to ever be able to efficiently use the resources we will come up with.
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Les Slater
9/23/2009 2:27 PM EDT
Re- krwada
I wonder what the 3d Internet will be like???
Its topology is already beyond simple 2d. Its nodes and connections exist in a spherical mesh on, below and above the surface of the earth.
It also has a fourth dimension, time stamps and beyond that reference to historical time.
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