Viewpoint: The importance of FPGA-to-ASIC solutions to accelerate CPU-based protocols

For many years, there has been a running debate about how to best handle the processing of protocols mid-way up the protocol stack in a data networking or enterprise storage application. Oftentimes this array of protocols is referred to as the data management layer. Algorithms in the data management layer typically include protocols such as encryption, compression, hashing, and complex searching.

For flexibility reasons, many system designs stick with off-the-shelf CPUs such as an Intel or AMD x86 processor running on a standard server motherboard. Other CPU-centric solutions deploy more embedded solutions using multi-function CPUs such as Freescale's Power QUICC processor, which resides on a plug-in PCI Express-based card. While these CPU solutions certainly provide flexibility, they often fall short of meeting high-end performance targets within the constraints of a product's cost and power budget.

For power and cost reasons, other system designs choose the fixed-function ASIC or ASSP-based approach. These solutions consist of PCI Express-based cards with an ASIC or ASSP that has a function set pre-determined by the card or ASSP provider. The hope is that when the ASIC is defined—typically two or more years prior to product launch—a common set of features can be defined, at a given performance and power, to capture what the system designers might need two years hence. While these solutions can often provide a great deal of performance at a reasonable cost point and with relatively low power, the mix of features and functionality often falls short of meeting the exact needs of system designers addressing present market application requirements.

FPGAs provide a great deal of flexibility. Today's FPGAs, from companies such as Altera and Xilinx, use cutting edge 45-nm silicon technology and offer a wide array of speeds and capacity options. They also offer high speed PCI Express interfaces embedded into the FPGA silicon, making them a perfect fit for PCI Express accelerator cards. While not as flexible as a CPU, an FPGA can be programmed to meet the exact needs of the system application. The feature set can be aligned with what the system designer needs and it can be implemented much faster than the typical two-year ASIC cycle. Often, within just a few short weeks a PCI Express-based protocol accelerator can be deployed with a feature set matching the needs of the market today. However, FPGAs by themselves can be quite expensive to deploy, and performance, while good, may fall a little short of the target.