Minimizing SoC Risk with Embedded Programmable Logic

Using embedded programmable logic can reduce the time spent on the verification of large system chips. With chips becoming increasing large and complex, nearly as much time is taken to verify a chip as to design it. Now, a designer can put a programmable-logic IP core on a multi-million-gate design. By placing the high risk design blocks in a programmable-logic core embedded in an SoC, the verification engineer is able to tune his silicon and make changes without having to spend months either simulating corner-case conditions or building and debugging FPGA prototypes.

In communications, bandwidth is the key driver for increasingly complex system chips. In these applications, 2-3 million-gate devices are common. The network processor is a term that has evolved to describe a new class of SoC networking devices. The author has encountered customers who are planning systems with devices in excess of 10 million gates. Other customers have planned complex multiprocessor systems in which a single system may include up to ten circuit boards, each with ten ASIC devices over a million gates in complexity, with individual chips having up to five-million gates. In such systems, the majority of such devices are for control within the system to optimize performance and broker conflicts between the processor and different datapath functions. The opportunity as semiconductor geometries move to 0.13 microns and below is to begin aggregating these complex, control-oriented devices with the processors in ever more complex system chips.

While much of the functionality built into system chips is generally comparable in complexity to systems comprising multiple components, the risk of designing a single device is greater. This increased risk arises from many sources, including:

1. The use of silicon IP from companies for major building blocks that are much less proven than traditional ASSPs used in systems
   
   
2. An order of magnitude increase in control-logic complexity from the use of multiple processors and parallel processing of many functions
   
   
3. A lack of design debug visibility into system chips versus traditional system-level lab debugging tools
   
   
4. The difficulty and expense of potential field upgrades.

Embedding programmable logic into these very complex devices of one to many millions of gates can greatly minimize the project risks. Embedded programmable logic adds other benefits, such as easy field upgrades and the ability to leverage a single development effort and prototype chip-debug effort across multiple designs in a product family. Many system-design teams have relied on extensive use of large farms of compute servers for simulation and multi-million-dollar chip-emulation systems for verification of their products to minimize the risk that they will have to go through multiple prototype chip cycles. Such cycles can add months to project schedules and millions of dollars to project budgets. Ironically, most of the design risk is typically constrained to a few major blocks of the design.

Embedding programmable logic has other benefits as well. Not only can you minimize initial design risk, but once programmable logic is within the chip, you can easily implement upgrades to accommodate various scenarios, much like downloading new software device drivers to your computer. When used to implement emerging or changing standards, as is the typical case in networking and wireless communications, the design specifications and development effort can proceed if blocks of the design likely to be affected are targeted to programmable logic. By taking such an architectural approach to the design, a company can obtain a large time-to-market advantage over competition that chooses to wait until standards are firm, which in some cases can take years. The alternative, choosing to proceed without embedded programmable logic, can lead to the inevitable redesign cycle with every change as the standards firm up.

As product life cycles shrink, more and more companies are engaging in parallel product-development programs. Development cycles can still often stretch to 18 months or more from architectural development to production shipments. Often products within a family share many similarities. By embedding programmable logic within ASICs or ASSPs, you can achieve product differentiation by simply programming in the differentiating product features within the various members of a product family. By designing these ASICs with this intent, the same chips can be used in multiple products, avoiding the multiple development efforts, verification cycles, and prototype chip-fabrication cycles of completely different chips.

From a chip timing and performance standpoint, clock rates continue to go up quickly, and interconnect delay becomes more critical. Characterization of block-level timing is more and more important as timing analysis becomes integrated into the development process earlier and earlier. Integrating programmable logic can best address the critical timing analysis of SoC designs when the programmable logic is in the form of a re-usable cell for which timing has been characterized in the target foundry process. Furthermore, there needs to be topology-specific extraction tools, which can provide the design-specific timing characteristic data after a block has been fully mapped to the embedded programmable-logic cell.