Beating the Bandwidth Barrier

Initial development for system-on-a-chip (SoC) development concentrated in two areas—high-speed data processing and lower chip cost. Designers achieved processing-speed improvements primarily through the use of faster microprocessor and DSP cores—today's highest speed processing engines run at hundreds of MHz. SoC developers obtained cost reductions largely by migrating designs to and developing new designs for smaller-feature silicon-process technologies.

Fueled by an exploding demand for consumer-oriented portable devices, lower power consumption entered as a third design target. Designers are able to reduce power through a combination of smart circuit-design techniques, improved system designs, and silicon-process enhancements. However, further development in these areas—speed, cost, and power—will not be sufficient by themselves for tomorrow's SoCs. Designers need to address increasing bandwidth requirements, with buses on the chip and in transferring data on- and off-chip.

Computational SoC cores, which encompass microprocessor, microcontroller, and DSP engines, do a wonderful job of taking in and crunching the data, and then preparing computed results for use elsewhere on the chip. Computational speed has become less of a problem than moving data in and out of the processing core. Transferring data to and from the core to other chip logic is part of the job of the chip's bus. A high-speed, on-chip, SoC bus needs the following attributes:

• The bus has to be able to "feed" the computing core at a fast enough rate so that the core does not sit idle.
• The bus must be able to rapidly transfer intermediate and final results between the core and certain embedded memories. These on-chip memories may be as large as several hundred thousand Kbits.
• Many SoCs have multiple processing cores, for example, a microprocessor and a DSP. The bus has to transfer data between these processing cores.
• The bus has to take processed data from a core and bring it to various types of logic blocks that will communicate with other off-chip system components.
• To take advantage of silicon cores or IP from several different sources, on-chip buses have to be able to deal with different types of core-communication protocols.

On-chip buses hence need three attributes—speed, flexibility, and bandwidth—to meet design-specific requirements. Flexibility for multi-core designs is often addressed outside of the core architecture, often with wrappers that go around silicon IP and act as a go-between from the IP to the bus. Speed may be limited by a silicon-process' interconnect parasitics and the physical implementation of the chip. This leaves bandwidth as the bus property with the most potential for meeting tomorrow's SoC-based system requirements.

There are two primary ways of achieving higher bus bandwidth: increasing the bus data-propagation speed, which may have process and/or layout limitations, or increasing the width of the bus. Going beyond the commonly used 32-bit bus—to 64 bits or beyond—costs you in routing complexity and, for a core-limited chip, chip size and cost. However, this is a necessary tradeoff to obtain the SoC performance that designers will need to meet some future high-speed SoC applications, such as graphics-centric Web appliances. To design wider on-chip bus architectures, designers need better design tools, more accurate timing models, and wider-word processing engines (you can use a wide bus on narrower-width processing cores, in a parallel processing configuration, at the cost of design complexity). However, increasing on-chip bandwidth solves only part of the high-speed data transfer problem.

The problem of transferring data between on-chip cores is mirrored by the difficulty of getting data on and off the SoC. Moving large amounts of data, such as that involved with video processing, between a chip and other system components requires high-speed I/O blocks on the chip. Silicon-IP designers are working hard to develop both high-speed serial- and parallel-data blocks. Gigabit-plus serial data links are effective up to a point. For some designs, it is more efficient to move data on and off the chip using wide-word parallel transfers. Parallel data links mean higher cost, both in packages and, for pad-limited chips, silicon size. Nevertheless, a wide-word parallel data path may be the only way for an SoC design to meet system bandwidth requirements.

Solving the bandwidth problem, both on- and off-chip, requires cooperative efforts among silicon foundries, chip designers, system designers, EDA tool vendors, and silicon-IP developers. To get high-bandwidth buses for handling fast transfer of large amounts of data you need continuing improvement in bus architectures and models, more efficient design tools, and innovative system design. Remember that having a fast processor hooked to a bus with insufficient bandwidth is just wasting processing power.