A Great DATE in the City of Lights for Chip Designers

The annual Design Automation and Test Expo (DATE), held in Paris, France March 4-8, 2002, proved to be an excellent venue for several companies to showcase their new EDA tools, silicon IP products, and services. While at the conference, I had the opportunity to review several interesting offerings in the areas of high-frequency design, silicon cores, and system-on-a-chip (SoC) design.

RF/High-Frequency Design
The communications market continues to drive tool and EDA tool development for RF analysis and simulation applications. As reported earlier, Applied Wave Research (AWR) has the Visual System Simulator 2002 (VSS2002) communication-systems design suite. The suite combines a discrete-time simulation engine, interactive top-down design environment using block diagrams, and a pre-defined library of over 200 core elements and mathematical primitives for developing complex communications systems that comprise both RF and DSP functionality. Other VSS2002 features include:

• Optional libraries for 3G, IS95, GSM, EDGE, 802.11, and other emerging standards
• Built in measurements for Power Spectral Density, Error Vector Magnitude (EVM), Adjacent Channel Power Ratio (ACPR), and Complementary Cumulative Distribution Function (CCDF)
• Support of several modulation schemes, including AM, FM, orthogonal frequency division multiplexing (OFDM), phase shift keying (PSK), mask shift keying (MSK), and quadrature amplitude modulation (QAM).

Ansoft has two tools"one new (Siwave) and one upgraded (Turbo Package Analyzer)"for signal-integrity (SI) and chip-package analyses. With RF designs at all integration levels becoming more complex and supporting higher frequencies, the value of Siwave lies in a combination of versatility and accuracy. The tool uses full-wave analysis to provide frequency- and time-domain analyses of very complex components, chip packages, and printed-circuit boards (PCBs). With its interfaces to several popular PCB layout-design programs, including Cadence's Allegro and Advanced Package Designer, Zuken's CR-5000, and Avant!'s Encore, you can use Siwave for simulating SI effects for entire boards or chip packages. Simultaneous switching noise (SSN), power and ground bounce, resonances, reflections, noise coupling between signal traces and power and ground planes, and impedance discontinuities are among the SI phenomena handled by Siwave. Along with 3D visualization, the tool also generates equivalent Spice models for additional simulations.

TPA 4.0 has been upgraded for improved analysis of chip packages such as flip-chip, chip-scale, and MCMs, the latter commonly used in network and wireless applications. The tool, working with Cadence, Avant!, and Zuken package-layout tools, works on an entire package and produces a lumped or distributed RLC model for any package lead or group of leads. Version 4.0 also simplifies crosstalk analysis for BGA package elements such as wire bonds, pads, vias, traces, solder balls, and power and ground elements.

Silicon IP
Several notable silicon IP (SIP) cores were discussed at the show. Saturn, the first product from Adelante's Galaxic DST Technology, is a reconfigurable and extendable soft DSP core that boasts some impressive numbers"0.25 mW/MHz power dissipation and a performance level of 420 MMACs/sec from a 0.18-micron CMOS process. Saturn employs a dual Harvard architecture and three-stage pipeline with 16-bit data and instruction words. In only 40,000 logic gates, the core comprises two 16-bit multipliers, four 16-bit ALUs, two address calculation units, barrel shifter, a program control unit, a hardware loop control unit, a saturation and shift unit, and a bit-manipulation unit. There are two data memories, each of which can be as large as 64 K words by 16-bits. Saturn is fully static, allowing it to run at clock frequencies from 0 to 210 MHz.

Saturn's instruction set consists of 16- and 32-bit instructions, with most instructions 16 bits wide, and targets wireless, speech recognition, and storage applications. The majority of instructions are executed in a single clock single, resulting in a compact code set that saves power and, due to reduced code-storage requirements, results in a smaller die size. Saturn's extendability results from three software and hardware extensions:

• Designers can expand the core's instruction set by as many as 256 application-specific, 96-bit VLIW instructions. This expansion can provide up to 12 operations in a single clock cycle, thus enhancing core performance for repetitive, compute-intensive operations.
• You can expand Saturn's datapath resources by adding application-specific hardware execution units. Each unit, written in an HDL, typically adds 1K gates or less to the core, becomes part of the core's hardware, and accelerates multi-cycle operations 10-30X.
• Adelante also has several stand-along co-processors to operate with a Saturn core. The co-processors operate independently from Saturn and have their own clock, buses, and registers. According to Adelante, each co-processor adds 500-5,000 gates, requires 10-1000 cycles to execute, and can accelerate DSP subsystem functionality by 20-2000X.

Amphion's CS6510 JPEG2000 hardware-accelerator core works with an embedded host processor to form a single-chip complete JPEG2000 encoding system. Advantages of JPEG2000 over JPEG include more image storage for a given amount of memory, image-quality enhancement without reprocessing the image, and simultaneous support of real-time lossy and lossless compression. For useful JPEG2000 links visit www.jpeg.org/JPEG2000.htm.

The hardware-accelerated Wavelet Transform-based core targets advanced still- and motion-image compression applications, such as 'dual-mode' still/movie-clip multi-megapixel digital cameras, 4G/3G wireless systems, medical imaging, office equipment, and surveillance. The CS6510 complies with the ISO/IEC 15444-1 standard JPEG2000 image-coding system, performing computationally intensive tasks such as wavelet transform, entropy coding, quantization, and data scheduling. Taking over these operations lets the system processor concentrate on handling tasks such as managing the user interface, audio processing, and output data formatting.

In a 0.18-micron CMOS process the CS6510, comprising 130K gates and 48 Kbytes of RAM, provides data-encoding rates up to 60 MegaSamples/second (MS/s) on 8-bit samples with real-time 'lossy' image compression ratios up to 50:1 (JPEG only supports compression ratios up to 25:1). The core also handles arbitrary image sizes up to 2³¹ x 2³¹ pixels, standard 'lossless' compression, flexible-image input formats, and a wide variety of grayscale and color imaging formats such as RGB, YUV, YCrCb, and CMYK.

Sonics' new MemMax Memory Scheduler is here to assist SoC designers in controlling memory subsystems for multicore chips using the company's SiliconBackplane MicroNetwork core. The MicroNetwork core manages communications between various silicon cores on a chip. MemMax improves the efficiency of controlling external memory (DRAM) from an SoC. An optimized memory subsystem consists of the MemMax scheduler, a conventional DRAM controller with an Open Core Protocol (OCP) interface, and external DRAM chips. MemMax schedules requests from different initiator threads received through a multi-threaded OCP interface on the MicroNetwork side. After scheduling, MemMax passes a sequential request stream to the DRAM controller through a single-threaded OCP interface. The controller operates as a conventional device handling the timing, protocol, and refresh requirements for the DRAM technology it is driving. Performing only the scheduling functions ensures the MemMax core is independent of specific DRAM-technologies. This allows designs employing the MemMax scheduler to utilize alternative DRAM memory controllers and technologies. You configure MemMax through a GUI that supports scheduling of up to eight request threads with three levels of service quality: priority, allocated bandwidth, and best effort.

SoC Design
Along with design tools and methodologies addressing SoC timing and signal-integrity issues, chip designers are now getting help in designing for low power. Sequence Design has launched their low-power/low-voltage design initiative, along with SIP power modeling. The company's NanoCool initiative is designed around a low-power chip-design methodology, similar to design methodologies for timing closure but with a goal of meeting low-power specifications for handheld and portable devices utilizing silicon technologies of 0.1 microns and below. The initiative's goal, according to Sequence, is to produce a design flow in which you can identify potential power consumption and distribution problems, fix these problems, and validation the fixes prior to expensive and time-consuming chip tapeout.

Specifically, NanoCool will help designers reduce leakage and dynamic power, perform noise analysis, repair noise problems, and optimize for timing along with meeting power constraints, all spanning design from architectural exploration through design extraction from the physical database. Sequence plans to work with SIP and EDA-tool vendors, along with end users, to accomplish the initiative's goals. Silicon Metrics has already worked with Sequence on power-modeling support and Virtual Silicon will make low-leakage SIP for qualification within Sequence's power-optimization design flow.

Within the NanoCool design flow, Sequence is adding SIP power models to the company's PowerTheatre tool suite. Complementing existing PowerTheatre tools for power analysis at the RTL and gate level, and pre-synthesis RTL power optimization, the new power-modeling capability lets you create detailed power models for silicon cores. The model will use the Advance Library Format (ALF) for power modeling, including stimuli vector activity, to produce a state-dependent macro power model of a core.

Also in the realm of power analysis is OFFIS Systems and Consulting's (OSC's) new version of ORINOCO, a software tool you use to optimize a chip's power consumption at the C/C++ or VHDL behavioral level, above RTL. Without going through a design-synthesis step, ORINOCO analyzes system specifications and then simulates and executes the code to produce execution and data traces based on real application data. These traces provide an internal control data-flow representation, used by the tool to estimate power for datapaths, finite state machines, clock trees, registers, memories, and other system blocks. The tool gives you estimated maximum and minimum power, based on a consideration of all possible algorithmic states, allowing designers to do "what if" power analyses prior to RTL code generation. Improvements in the new version of ORINOCO include controller power estimation, an improved wire-length model accounting for global floorplanning considerations, and better resource scheduling for improved accuracy.

Celoxica's DK1 C-variant-to-hardware design suite got a facelift for the Paris show. DK1.1 works on designs specified in Handel-C, an ANSI-C derivative that includes provisions for timing, concurrency, flexible-width variables, and resource allocation geared towards hardware design. The design suite includes design entry, simulation, and synthesis, letting software engineers develop hardware to support the design, validation, refinement, and implementation of complex algorithms. New features in DK1.1 include improved system-level hardware/software co-design, co-simulation support for ARM and PowerPC embedded processor cores (in Xilinx Pro and Altera Excalibur devices), better synthesis, enhanced area and timing analysis, more compact VHDL generation, a new Verilog output capability, faster simulation (up to 100X), and support for Actel, Altera, and Xilinx programmable-logic devices. A mixed-language capability lets you work with C/C++ and Handel-C concurrently. For example, you can use a C/C++ testbench to verify a Handel-C design.

Addressing timing closure for 0.13-micron and below chip designs, Cadence has enhanced its recommended digital-chip design flow with the SoC Encounter tool bundle. SoC Encounter combines the virtual prototyping and hierarchical partitioning capabilities of First Encounter, from recently acquired (December 2001) Silicon Perspective, with Cadence's synthesis/place-and-route (SP&R) and signal-integrity tools. Touting a chip capacity of up to 30-million gates, SoC Encounter lets a designer:

• Read an RTL or gate-level netlist and construct a virtual prototype, representing the chip's timing, routing, power, size, and signal-integrity issues (physical feasibility analysis)
• Partition the chip into hierarchical blocks with pin assignments and timing budgets
• Perform physical synthesis, with detailed placement and routing at the block level, to meet timing constraints
• Do a final design assembly, analyze for SI violations, and repair such violations.

SoC Encounter puts Cadence on the same playing field with Synopsys and Magma Design Automation, both of whom have tool suites for a similar RTL to GDS-II (physical database) digital chip design flow.

Dealing with SoC design teams spread among different locations and time zones is a major problem in efficiently designing and verifying complex chips. Synchronicity continues to develop new and enhanced design-collaboration software to help with the difficulties of enterprise engineering on the chip level. The company had three announcements around the time of the DATE conference regarding their Developer Suite of design collaboration and management tools and CAD HelpDesk, a standalone support application to assist engineering teams working on projects involving large numbers of products.

Developer Suite v3.2 has added Lightweight Directory Access Protocol (LDAP), simplifying central administration of access control to a company's internal online resources. Other noteworthy enhancements include live backup, better handling of very large files, improved data caching for local sites, and the addition of Linux, AIX, and Windows 2000 support to existing Solaris, HP-UX, and Windows NT ports. The SoC Developer Suite now has a Hierarchical Configuration Manager (HCM), which lets you work with design data concurrently at the chip, block, and cell level. HCM lets you define hierarchical relationships within the collaborative software that more closely matches a chip's design and reuse hierarchy, simplifying an engineer's management of a design's total database. The CAD HelpDesk is a centralized support system providing a common knowledge base and communication channels between central analysts and diverse engineering personnel. This support assists in several areas, such as resolving design and coordination problems and questions, providing a history of key events and communications, routing of design issues, and providing necessary reports and metrics.

Test, Design-for-Test Issues
Along with increasing SoC speed and complexity comes the unenviable problem of testing these devices. SoC test and design-for-test (DFT), unfortunately, continue to progress at a slower rate than does SoC design. This "design gap" results in test cost being an increasing percentage of total chip-manufacturing cost. DATE exhibitors included several companies showcasing products to help overcome test and DFT obstacles, in particular, the barrier separating chip simulation and manufacturing test.

Embedded Test 4.0 (ET 4.0) is LogicVision's solution for developing and implementing embedded test into SoCs. ET 4.0's useful features include a vector-less transfer of embedded-test data from design to manufacturing (simulation to test vectors) and ATE-independent user interfaces with an API wrapper. ET 4.0 includes provisions for flat and hierarchical logic, memory, programmable memory, and PLL built-in self-test (BIST) along with core tests.

Also addressing the chip-design-to-test bridge is IMS's TestDeveloper test-automation software package. With the help of a timing-diagram-based interface, TestDeveloper manages scan and functional test patterns, generating timing patterns from chip simulations for use by ATE platforms. The software is compatible with several ATE platforms and supports STIL, WGL, Verilog, and VHDL.