Hard Choices Among FPGA Hardening Options

Field-programmable gate arrays (FPGAs) may be the greatest boon to hardware developers ever. They're great because they allow an engineer to hide his mistakes. No matter how badly the design goes wrong, it's easy to just erase the FPGA, reprogram it, and try again. Like using an Etch-a-Sketch for chip design, FPGAs appeal to the budding—but not yet perfect —designer in all of us.

The downside of FPGAs, of course, is their cost. Although designers love them, purchasing managers often hate them. They're single-sourced, expensive, and absolutely necessary to any product design that uses them. Like any high-cost, high-value component, they hold the customer over a barrel. Once they're designed-in, there's no easy way to design them back out. Using FPGAs is like using heroin: the first sample may get you hooked but after that it gets very expensive.

For the past fifteen years the solution to this problem was to suffer. Xilinx, Altera, and the other FPGA makers simply didn't offer any alternative. Either you bought their FPGAs or you totally redesigned your product to eliminate them. The first option was expensive but the second option was more expensive. And who can blame them? The FPGA makers are in the business to sell FPGA chips; they have no interest in helping customers reduce consumption of their own product.

Now the major FPGA makers have seen the light. Altera and Xilinx both offer "hardened" versions of their normally "soft" FPGA chips. These offer a nice middle ground between the total flexibility (and maximum cost) of an FPGA and the negligible flexibility of a fixed ASIC or other fixed-function chip. These two companies, which normally mirror each other's moves closely, took totally different approaches to their hardened chips. The battle now will be over which approach customers like better.

So what's the catch? The disadvantage of EasyPath is the customer can no longer change his design. Once you switch to EasyPath you're committed to freezing the hardware design that goes into it. That's not as big a drawback as it might sound, and if you do change your design you can always switch to different EasyPath parts. Your design freedom isn't frozen forever, only until your inventory of EasyPath chips runs out.

How does Xilinx do it? The company is basically selling its defective chips. With any semiconductor manufacturing process, some chips come out bad. Some of the batch is burnt, so to speak. All chip makers guard their "yield" percentage numbers very closely, but an average yield is from 85% to 98% good chips. The rest are thrown away, ground into sparkly dust, or made into tie tacks and executive paperweights. The trouble is, chip makers don't know which chips are good and which ones are bad until the very end of the manufacturing process. By that time, they've paid for all the materials and labor, so bad chips cost just as much to make as good chips. Naturally, the good chips have to carry the cost burden of all their siblings that didn't make it out the door.

The situation is somewhat worse for FPGA chips because they're so flexible. The average FPGA dedicates about 90% of its silicon to programmability; only about 10% is actual useful logic. By any measure, that's a horribly inefficient design and no sane chip designer would have thought of it, yet FPGAs sell quite well. It's as if every new car carried around ten times its own weight in excess scrap steel. Hardware engineers pay a terrible price for all that flexibility.

Xilinx has turned this necessity into a virtue. Instead of tossing out all the bad chips, it sells them. EasyPath is basically the company's name for chips it's fished out of the Dumpster. Sold at a discount, these chips find ready homes with designers looking to reduce their costs.

Xilinx saves its customers that trouble by rooting through the reject pile for them. Once customers decide to go the EasyPath route, they provide their design file to Xilinx, which then uses that design as a filter for selecting parts. If a given chip's defect(s) does not affect the customer's design, it's approved. Even if the chip doesn't work for this customer, it might be acceptable to another customer. The net result is that the customer gets a cheaper FPGA and Xilinx gets to sell some otherwise abandoned chips. Everybody wins.

Although a customer could alter his design down the road, there's no guarantee that the updated design would work in the same EasyPath devices. It might be that the newer design uses a few gates that weren't used before, or changes the signal routing somewhat. Xilinx can't guarantee that the new design will work in the old chip. It might be okay—in fact, it's pretty likely that small changes will work just fine—but it would be risky to bet on it.

Altera's new product line is called HardCopy II and as the name suggests, it follows on the heels of the company's earlier HardCopy family. Altera knows full well that its FPGAs devote enormous amounts of valuable silicon to reprogrammability, with only a tiny fraction left over for real logic, so why not eliminate that waste at the source? Rather than salvage chips with defects somewhere in that 90%, Altera eliminated the 90% overhead altogether. HardCopy II chips are therefore much smaller and faster than their completely programmable brethren.

Altera completely redesigned and re-architected the internals of its HardCopy II devices so that they look nothing at all like normal FPGAs. Each programmable logic block and lookup table (LUT) in the FPGA is replaced with a small core of logic gates that can perform similar functions but in a completely different way. The result is the same but the method is different. Similarly, HardCopy II replaces the FPGA's programmable interconnect with a much smaller and more efficient array of copper and aluminum wires, many of which aren't even placed or routed until the customer design has been fixed. HardCopy II is, for all intents and purposes, a custom ASIC. It's designed specifically for one customer and requires mask changes at Altera's foundry partner. The difference between HardCopy II and a "real" ASIC is cost—and flexibility. Converting from an FPGA to a HardCopy II equivalent doesn't cost millions of dollars like designing an ASIC would. And even though Altera's chips are flexible, they still bear the blocky logic characteristic that's synonymous with FPGAs. It's not quite the same as designing your own chip from scratch.

This total redesign means that Altera's HardCopy II chips are considerably faster then their programmable counterparts. That's both good news and bad news to hardware engineers. More speed is usually a good thing, but some designers don't welcome change to a working design. Some chip designs may run twice as fast as before, according to Altera. While most designers would kill for that kind of improvement—at lower cost!—it still excludes a certain class of engineer. HardCopy II chips also consume less power and give off less heat, two other benefits of the redesign effort. Pinouts remain the same, naturally, so customers can drop a HardCopy II chip into an existing socket without worrying about physical incompatibilities.

For its part, Xilinx charges only about $75,000 in nonrecurring engineering (NRE) fees. Of course, the company has to do very little work to justify that kind of money, certainly less than Altera does when it customizes chips for its customers. This makes EasyPath the easier path to follow for low-budget design teams.

If you want, Xilinx will test multiple designs at a time to determine which EasyPath chips are suitable and which aren't. This allows you to buy one batch of chips for two (or more) different designs or unrelated projects. Xilinx simply selects the superset of chips that support the supplied designs.

Xilinx's EasyPath seems like the simpler, less troublesome, and less expensive option of the two. Your design will behave exactly the same way before and after the transformation. Apart from the price tag, you'd be hard pressed to tell the difference between a conventional Xilinx FPGA and an EasyPath replacement. Your purchasing manager will thank you and your engineering team can move immediately on to some other project.

Altera's HardCopy II, on the other hand, offers some compelling advantages. The new chips will almost certainly be faster and more power-efficient, maybe by a factor of two. That's a pretty enticing way to speed up a high-volume chip design. Dropping power consumption is bound to be a good thing, too. If you don't want the speedup, by the way, you can insert delay buffers to deliberately slow the design and more closely mimic the timing of an FPGA. It's not perfect but it provides an option for projects that have already been fined-tuned.

On the downside, Altera's quarter-million dollar NRE fee will prevent all but the most sober customers from considering HardCopy II. You'd have to save a lot of money per chip, or buy a lot of chips, to amortize that down payment. There's also the added design time to consider. Although the conversion process from FPGA to HardCopy II is straightforward, it's not a push-button job. It requires some time and talent to render a successful conversion and the newer, faster chip might force some other hardware changes in the system. Even software might have to be tweaked to accommodate the improvements.

In the end, it's still going to come down to the small details. Which FPGA architecture do designers prefer? Which tool chain are they familiar with, or which salesperson took them to lunch last? The battle between FPGA titans, and now between their hardened offspring, shows no sign of letting up.

Jim Turley is an acknowledged authority on microprocessor chips, embedded systems, semiconductor intellectual property, computers, and silicon technology. He is the author of seven books, Editor-in-Chief of Embedded Systems Programming magazine, publisher and principal analyst of Silicon Insider, past editor of the prestigious industry journal Microprocessor Report (a three-time winner of the Computer Press Award), and is a regular speaker at industry events. He is frequently quoted in The Wall Street Journal, New York Times, San Jose Mercury News, and appears regularly on television, radio, and Internet broadcasts. His email address is info@jimturley.com.