Partitioning an ASIC Design into Multiple FPGAs

Most of today's system-on-chip (SoC) designs rely on field-programmable gate arrays (FPGAs) as a way to accelerate verification, start software development early and validate the whole system before committing to silicon. The FPGA may be an intermediate or, because tough economic realities cannot justify $1M+ in non-recurring engineering charges for an ASIC, initial implementation platform for the SoC design.

Today's FPGAs are large enough to contain a complex system-level design. It's practical, however, for these designs to be partitioned among several FPGAs for various reasons. For example, you may invariably need external components in your system. Also, using several smaller devices can enable a more cost-effective solution than using one big FPGA.

But, integrating your design into several FPGAs can create interesting partitioning problems, especially for larger and/or highly connected designs.

What are the Major Partitioning Considerations?

The most obvious problem for any design is the answer to the question: Will it fit into your FPGA prototype? If you have a very small design, you may fit everything onto a single, large FPGA and you technically won't have a real partitioning problem.

Figure 1: ASIC design start sizes

A note of caution: even though you may think that your design fits based on the ASIC gate count, your design may still need to be partitioned because of the resources available on the target FPGA. Memory or DSP-intensive ASICs frequently fall into this category of design.

Based on the current design sizes as shown in Figure 1, one-third to one-half of ASIC designs will fit into one of today's large FPGAs. Assuming that you have a bigger design and partitioning is required, you need to carefully estimate the number of FPGAs required in your prototyping hardware.

When you must partition, the three big concerns to keep in mind are:

1. Which blocks need to fit into which FPGA so that you do not exceed the capacity or other resources of the FPGAs in your hardware-prototyping system?
2. How do you interconnect the FPGAs? Most ASIC designs will exceed the number of available I/Os in the FPGA. Pin availability is further compounded by trying to meet timing.
3. Finally, ASIC designs often include elements that need to be converted to an appropriate form for an FPGA implementation, such as ASIC memories or gated-clock tree structures.

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