Using an FPGA to tame the power beast in consumer handheld MPUs

The consumer handheld market is growing by leaps and bounds. With more processing power and increased support for more applications, portable products are cross-pollinating with traditional computing systems even as the product life cycle has decreased considerably in this market segment. As a result, especially in this era of economic slowdown, it is imperative that new products meet the time-to-market window to gain maximum acceptance. A decrease in product life cycles requires a reduced development cycle and an increased emphasis on reusability and reprogrammability.

The emerging handheld market is also seeing interesting trends in which each individual device in a family has lower volumes but there is more customization across the series of devices, effectively upping the total unit volumes. The key challenge then becomes how to develop a system that is widely reusable and also customizable.

These requirements have led designers increasingly to turn to the FPGA for handheld-product development. The FPGA has become more powerful and feature-rich, while gate counts, area and frequency have increased. FPGA development and turnaround cycles are considerably shorter than those of custom ASICs, and the added advantage of reprogrammability can make the FPGA a more compelling solution for handheld embedded systems.

In an ASIC- or an FPGA-based design, designers must take certain performance criteria into account. The challenges can be stated in terms of area, speed and power.

As with the ASIC, vendors are taking care of the area and speed challenges in FPGA design. With increased gate counts, the FPGA has more area and size to accommodate larger applications, and tools include better algorithms to utilize the area optimally. For example, technology advancements with newer standard-cell libraries have led to FPGAs achieving higher frequencies.

The newer and better FPGA technology brings with it a whole new set of challenges for the designer. Power utilization is one issue that moves to the forefront when designing an FPGA-based embedded system for a handheld or portable device.

A typical embedded system consists of a processor, memory, standard interfaces like USB, SPI, I²C and so on, along with peripherals such as liquid-crystal display, audio-out and the like. The heart of the application still resides in the processor and the processor interfaces, with various peripherals using onboard connections. The performance of the system depends on the performance of the processor, which has a very standard architecture and is not easy to customize.

The processor may also end up utilizing its activity time in processing information from a slower peripheral (for example, reading data from a slower ADC audio on an I2S interface). Although the processor usage may reach 100 percent in this case, the device is not doing microprocessor-centric activities but is working at a significantly lower performance level. Irrespective of its core frequency, the microprocessor must wait for the data from a slower clock. This also results in higher power consumption, as the processor is showing full utilization. The result is lower battery life along with larger heat sinks or fans for cooling, eventually affecting the reliability of the entire system.