Clock sources with integrated power supply noise rejection simplify power supply design in FPGA-based systems

Power hungry systems cannot be free of power supply noise. In general, system designers try to use low noise linear power supplies whenever possible. However, excessive power dissipation usually prevents the use of linear regulators. When using a linear device, regulating from 3.3 V input to 1.8 V output is only 54% efficient regardless of the load current. Low conversion efficiency burns power in the regulator instead of the load and makes linear devices unsuitable for many high performance applications.

The use of low dropout regulators (LDOs) helps improve efficiency by reducing the input to output voltage difference that the regulator produces. For example, 2.5 to 1.8 V regulation yields 72 % efficiency for all loads. This is generally a good practice for loads up to 500 mA. However, when the load consumes 1 to 3 A of current, LDOs are less helpful. When a regulator enters dropout, it no longer regulates effectively. Its pass element behaves like a resistor, unable to respond to changes in load current or input voltage. This effect diminishes the noise rejection of the regulator, defeating the purpose of using it to provide power to sensitive circuit blocks. To maintain good regulation and noise rejection, LDOs must be powered by considerably higher input voltages than their dropout specification dictates, decreasing efficiency. To avoid dropout conditions, multiple LDOs can be placed in parallel to reduce the load current through each regulator. Complicated and costly, this alternative is not an attractive solution.

A more practical way to increase efficiency and maintain regulation over a wide load current range is with the use of switching regulators. The high 85 to 95 % efficiency of switching regulators often makes them the only power conversion alternative for FPGAs. The boost in efficiency comes with a noise penalty, with as much as 50 to 100 mVp-p of peak-to-peak voltage ripple. Due to the high power consumption of FPGA logic and I/O, switching ripple lower than 50 mVp-p is generally expensive and impractical.

Another noise source is the FPGA itself. The fabric system clock may run at tens to hundreds of megahertz. When high power digital logic operates, it generates noise transients that ripple through the various power planes. Fast transients create high energy spurs that power supply filters struggle to smooth out. Since most power supply decoupling is optimized to present low impedance around one or a few frequencies, it is difficult or even impossible to clean up all high frequency noise on the power supply rail. This noise tends to propagate to other subsystems through the power supply, especially those in close proximity with the FPGA.