Power-aware FPGA design (Part 1)

Part 1
– Abstract
– Introduction
– FPGA Power Components and System Profile
– Fighting Static Power
– Fighting Dynamic Power

Part 2
– Fighting Dynamic Power (continued)

Part 2
– Fighting Dynamic Power (continued)
– Proposed Power Reduction Methodology
– Conclusions
– References

Abstract
Power consumption requirements in new autonomous, multimedia-savvy consumer products that can store, transmit, and receive data have catapulted system architects and board and chip designers into a new realm. Even when designers attempted to reduce system power consumption, their approaches were not comprehensive and focused enough to achieve optimal results.

This two-part article covers several aspects of FPGA power consumption: FPGA architecture and features, the power components associated with FPGAs, and the FPGA process technology development itself. It also provides a new look at power dissipation numbers, and questions the traditional methods of estimating and measuring power. We show that design and system power profiles are keys to successfully reducing power consumption.

Introduction
The latest process technologies revealed a troublesome issue: the dramatic increase in static power. This issue is worse for FPGAs than for ASICs. Today, power comes to play in bill-of-materials (BOM), board design, chip design, testing, and production flow.

ASIC and ASSP vendors dealt with power in various ways; however, FPGA vendors have only recently introduced novel and power-friendly FPGA architectures and features. A key feature is the availability of various power modes and power voltages. For example, Actel IGLOO and ProASIC3L FPGA families feature various power modes with state saving (On, Static, Idle, and Flash*Freeze modes), as well as operation at 1.5 V or 1.2 V for both the core and the I/Os.

Similarly, Altera announced a more power-friendly derivative family of the Max' II, called Max IIZ [MaxIIZ2007]. Xilinx led the charge in 2006 with the CoolRunner CPLD families [CoolRunner2006], and now offers power derivatives of its Virtex families.

All three vendors provide several analysis tools to help users estimate the power consumption at different stages of their design cycles [BADAZ2008]. Efforts to improve the backend tools also help reduce wasted power [Libero2009]. This article aids power reduction by clearly defining and describing FPGA design techniques and their impact on power and energy consumption.

The goal of this article is to examine each design step and each component of system power with the purpose of providing techniques to reduce wasteful power consumption. These techniques cover system partitioning, chip design, and board layout. Chip design includes RTL coding, DesignWare arithmetic architecture power profiling, and place-and-route hints.

Some of these techniques may initially seem "old hat," but they have been revisited to fit the profile of applications required by most of the new consumer products targeting low-power FPGAs. In addition, available power modes are exploited to minimize further power consumption, energy, and battery life.

A new look at power numbers
While measuring the actual silicon power-consumption numbers of several designs, we came across different implementations of the same basic design. Each of these implementations often had a different power number associated with them.

The analysis of these differences in implementation area, timing, and power attributes revealed that considering simple, single-cycle power numbers was misleading and even erroneous. Indeed, some implementations had the worst power consumption if we considered only one clock cycle and would have been abandoned if we did not consider the data arrival pattern and the potential use of power modes or power-down options.

For example, one implementation of a design was architected to perform computation on a data packet in one cycle, while two others —apparently more power-friendly implementations— required 6 and 12 cycles, respectively, for the same computation. Based on the input data rate, the apparently power-hungry implementation could completely shut off the computation engine for 5 or 11 cycles and save a lot more energy (increasing battery life) than the two other implementations.

The targeted FPGA, an Actel IGLOO device, offers a sleep mode, called Flash*Freeze mode, which allows a drastic reduction in both static and dynamic power while retaining the registers and RAM states. Entering and staying in this mode allows the user to save power and battery life. To illustrate this, we created two architectures for a simple DES design: one serial implementation required 16 cycles to complete data processing, while a parallel implementation processed the same data in a single cycle. Table 1 provides the power results for a 100 MHz clock frequency.

Table 1. Attributes of serial vs. parallel DES implementations.

The message is to consider the dynamics of the arriving data patterns and the possibilities of exploiting the FPGA power modes. In addition, FPGA designers need to consider architectural options that target not only absolute power numbers for a particular clock cycle, but also the energy per computation. In summary, designers need to consider the big picture instead of performing the typical narrow interpretation of power numbers.

FPGA power components and system power profile
FPGA Power Components
Several criteria are used when selecting an FPGA from the abundant offerings available in the market. Cost, capacity, performance, features, and packaging are usually the main drivers in a system architect or designer's choice of one FPGA over others. With the rise of power-conscious applications in the portable consumer, medical, and even military market segments, power is getting a higher rank in the priority list.

Everyone is familiar with the traditional static and dynamic power present in ASICs or FPGAs. However, not everyone knows that, unlike ASICs and nonvolatile FPGAs, volatile FPGAs have two additional power components: the configuration power consumed during the programming at system power-up and the inrush power dissipated during the device functional power-up, as depicted in Fig 1.

1. Volatile vs. nonvolatile FPGA profiles.

FPGA- based board designers must account for the configuration and inrush powers while sizing their power supplies and selecting batteries. Despite the efforts of SRAM-based FPGA vendors to reduce the inrush and programming components, these are still present and have a severe negative impact, especially when several FPGAs are populating a single board or powered from a common supply on different boards. This additional power dissipation is even more serious for systems with frequent On/Off cycles and must be considered when estimating battery life.

In addition, volatile FPGAs require an external boot PROM for configuration storage, which adds to the overall power dissipation. Even though some vendors have embedded a large flash memory within the same device, the additional storage power is still present.