How to design portable handsets using CPLDs

The emerging need for flexibility
Using an ASIC or ASSP will typically meet a design project's specifications for functionality and power consumption. However, there are other factors design groups targeting the consumer market must take into account. And a chief emerging factor is flexibility. Indeed the consumer world is rapidly changing and features your team envisioned at one point in time can become obsolete within a matter of months, as you and your competitors react to ever-changing technologies and market dynamics to deliver differentiated solutions.

As the consumer electronics business becomes much more competitive, design teams need to make design choices that will allow them to produce the right products at the right time to ultimately help their companies sustain and hopefully build market share. But this need to be agile in the market and makes picking the correct ASSP or designing the right ASIC a very difficult task.

Today's designers are now looking beyond the fixed architecture of ASICs and ASSPs to discover the innate design flexibility and time-to-market benefits of programmable logic. Today's low power CPLDs offer portable device designers a viable alternative to standard cell technology and provide some of the lowest cost, lowest power solutions.

Various CPLD families are now priced low enough that they are comparable in price to discrete logic devices but give design groups the added benefit of modifying their designs quickly to seize market opportunities.

Let's examine ways to expand beyond the limitations of today's ASIC/ASSP portable handset solutions, with simple, cost-effective, low-power programmable logic using CPLDs. As most handsets today are OMAP-, XScale- or i.MX-based designs, we'll describe how CPLDs can offer solutions to several problems that commonly pop up with these portable mobile platforms.

Level translation
A very common problem designers encounter today is interfacing two chips that have different voltage requirements. Memory vendors typically do not make memories at every voltage level, yet MPU vendors typically offer devices at several voltage levels. Design groups can overcome this problem by using level translators, but level transistors are expensive and often more area in the system, which can add cost to the design. Using a CPLD is a better solution and offers substantially greater flexibility. Many CPLDs are capable of translating between two voltages, and some can handle as many as four.

Some CPLDs' I/O banks easily translate between voltages ranging from 1.5V to 3.6V in a single chip, as shown in Fig 1. But CPLDs also have the added benefits of programmability. You get that same translation as part of the whole package, which means you get a bundle of logic, flip-flops, power reduction resources, and I/O buffers frequently priced below level translator chips.

1. CPLD-level translation of TI OMAP signals.

Pin expansion
In general, high pin-count ASICs are more expensive than low pin-count ASICs. If your design project's logic needs dictate a low capacity, but your I/O requirements dictate a high capacity, you may be paying for logic you will never use to gain the pins. One solution to this is adding a CPLD to operate as a "pin expander," as shown in Fig 2.

2. CoolRunner-II CPLD pin expansion of XScale processor.

The basic idea is to identify GPIO pins that typically operate at a slow speed. Then, rather than assign ASIC pins to them, attach the CPLD pins to the slow-moving GPIO signals, serialize the signals, and import them to the ASIC on fewer net pins. You can perform serializing/deserializing through simple, efficient shifting, and can drop the pin counts dramatically on expensive ASICs.

As an alternate viewpoint, OMAP, XScale and i.MX processors provide specific pin mixes to support the applications their vendors deem appropriate. But you don't have to strictly follow their advice, which some deem as limitations. CPLD pin expansion permits you to create your own GPIO pins of assorted voltages and additional capabilities (such as pulsing, PWM, or individually 3-stated).