Strategies for minimizing Xilinx implementation tool runtimes

This document provides tips, techniques, and new options for controlling runtime in the Xilinx ISE Design Suite 10.1 release. The first section places the FPGA design cycle in the broader context of system development. It highlights the steps that typically require fast implementation runtime and – for each step – what the design properties are. The second section introduces the ISE 10.1 algorithmic improvements and provides a description of the new flows and options available for controlling software runtime. The third section lists a set of strategies that may be used at each stage in the development cycle to improve runtime.

Why we need faster implementation tools
A typical system development process is illustrated in Fig 1. The FPGA development cycle is grouped into three phases. The right-hand column highlights runtime requirements associated with the FPGA software for each of these phases.

1. System development cycle with FPGA software runtime expectations highlighted in yellow.
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We can see that the design complexity in terms of logic and constraint varies across the different stages in the FPGA development cycle. Therefore, the FPGA software algorithms and options must be tailored to meet these varied expectations.

In addition to the design logic being vastly different depending on the project completion level, trying to achieve one goal – runtime reduction in this example – often comes to the detriment of something else. In the FPGA implementation software world, optimizing algorithms for runtime can negatively impact maximum achievable performance, power consumption, or logic area use.

With each software release, many customer designs are run through the ISE design tools, tuning algorithms and options to statistically exceed previous releases. Thus, new algorithms, flows, and user-controlled options are included in the 10.1 release.

What's new in ISE Design Suite 10.1?
The following sections describe changes that influence application runtime in the ISE 10.1 release.

Place-and-Route algorithm changes The place-and-route algorithms are constraint-driven. This means algorithms applied to a design are dependent on the estimated timing, area, location, and power performance compared to user-defined constraints. Therefore, the next implementation algorithm step depends on the margin between the requirements and the implementation status. It then becomes obvious that user-applied constraints – as well as software performance estimation accuracy – have a tremendous impact on runtime. Inaccurate software estimation can lead to wasted runtime due to more optimization than is required to meet the constraint. Overzealous use of constraints may force the software to attempt to meet constraints that are at (or beyond) the device capabilities. To this effect, the ISE 10.1 packer, placer, and especially the router timing estimation engine, have been improved for early detection and reporting of placement situations not routable in the given constraint environment. This increase in timing estimation accuracy saves ISE runtime.

These enhancements apply to all FPGA architectures and provide quality of results and runtime benefits, as shown in Fig 2. Gains are most significant for medium-to-tough timing constraints, for example, designs for which constraints are at or slightly above levels that the place-and-route tool can deliver.

2. ISE 10.1 provides faster runtimes for medium-to-tight constraints compared to ISE 9.2i.
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New design goals and strategies option
The Design Goals and Strategies option in ISE 10.1 provides designers with an easy way to control implementation tool settings so as to achieve best results based on their design goals. Predefined design goals in ISE 10.1 are Balanced (the default), Area, Minimum Runtime, Power Optimization, and Maximum Timing Performance. Each of these goals provides associated strategies. A strategy is a set of implementation tool settings. This release provides a verified set of default goals and strategies for each supported device family. A designer can edit and create their own goals and strategies to address specific needs. They may also save them and apply them to another project. They can right click on any item in the Processes window, or go into the Project > Design Goals and Strategies... menu to access this feature.

SmartCompile flows
SmartCompile technology helps FPGA designers realize dramatically faster runtimes. SmartCompile comprises SmartGuide, Partitions, and SmartPreview:

• SmartCompile – SmartGuide: This flow, first introduced in ISE 9.1i, saves runtime when re-implementing a design after a change by reusing the maximum amount of placement and routing information. The primary objective is to achieve the performance targets; therefore, it is best to work with a previous implementation that has met all timing constraints. SmartGuide is a convenient feature because it does not require a specific methodology or constraint change. Typically, a designer can expect a 1.8x runtime reduction. Bigger runtime savings are achieved when netlist logic, modified constraints-applicable elements, and routing structure changes are smallest. Timing-critical path changes also have an influence on runtime. 
   
• SmartCompile – Partitions: This feature enables quick implementation runtime for obtaining post-implementation analyses and conclusions, which designers can share quickly with their development teams. Throughout the development cycle, designers will find situations where, after design changes, they must re-implement only a portion of the design, and meeting timing constraints on the modified design portion is not the primary objective. In such cases, they should consider SmartCompile – Partitions. For Partitions, the primary goal is to re-implement only the modified design partitions, exactly preserving previous implementation results for unchanged partitions. At the same time, this direct "copy-and-paste" of the unchanged partitions provides appreciable runtime savings. 
   
• SmartCompile – SmartPreview: This feature lets a designer interrupt the router process using the CTRL+C keyboard combination. SmartPreview generates a menu with options that save the design database and allows a designer to decide whether or not to let the tool continue routing. This database snapshot can be very useful in saving runtime at different stages in the design cycle, as follows: 
   
  • Timing and congestion analysis: Opening this database snapshot in the Floorplan Editor or the Timing Analyzer allows a designer to detect and analyze congested or problem areas early in the implementation process. While the design is still running, a designer can reconsider the clocking scheme and clock placement. They could also decide whether there are over-constraining placement constraints, such as tightly packed area groups, or paths covered by non-applicable constraints, such as false paths or multi-cycle paths. 
     
  • Program and debug design portions in the lab: Designers can perform verification on the parts of the design that already meet timing and also on the other parts of the design, if their setup allows operating the device at a lower frequency. 
     
  SmartPreview saves runtime and improves productivity by enabling analyses typically done only after place-and-route tool completion.