Wavelet data hiding using Achterbahn-128 on FPGAs

This paper proposes a new approach for data hiding in which the embedded signature data is reconstructed without knowing the original host image or using constant data size. The signature data is encrypted using the Achterbahn-128 stream cipher before embedding it in the wavelet coefficients. Finally, the data hiding system is implemented using FPGA technology. From the simulation results – which are applied to the MATLAB program in order to see the output image (the "stego image"), we can say that the human eye cannot observe the difference between the original image and stego image.

Introduction
In the present era of computers and fast communication, one needs to protect communicated information (message or plain text) from unauthorized users while sending it through any electronic media. One such technique to protect the data is steganography. Data hiding is also known as steganography (from the Greek words stegano, meaning "covered", and graphos, meaning "to write").

Steganography consists of techniques to allow the communication between two persons. It hides not only the contents but also the existence of the communication from the eyes of any observer. These techniques use a second perceptible message, with meaning disjoined by the secret message. This second message works as a "Trojan horse" and acts as a container of the first message [1,2].

New technologies such as information networks require more and more sophisticated strategies in order to prevent the privacy of messages. In this context, digital images (also audio streams) are excellent candidates to be turned into "containers" for messages, since the bits forming a secret text message can be superimposed – as slight noise – to the bits employed for coding the image.

Historically, the first instance of the use of steganography is found when the Greeks received warning of Xerxes' hostile intentions from a message underneath the wax of a writing tablet [3,4]. The Chinese practiced steganography by embedding a code Ideogram at a prearranged place in a dispatch. By comparison, medieval Europe utilized grill systems in which a paper or wooden template would be placed over a seemingly innocuous text, highlighting an embedded secret message.

The scientific study of Steganography can be traced to Simmons who formulated it as the "Prisoners Problem" in 1983. In this scenario, two prisoners (Alice and Bob) wish to devise an escape plan. However, all their communications pass through the warden (Willie) and if he detects any encrypted messages he will frustrate their plan by throwing them into solitary confinement. So they must find some way of hiding their cipher text in innocent-looking cover text. Also, they must ensure their plan does not become corrupted or destroyed by their transmission channel.

In this paper, a data embedding technique is proposed for embedding a significant amount of data in digital images while retaining high perceptual quality. The scheme employs digital communication techniques to achieve high robustness to standard image processing operations. Information is embedded in the wavelet domain by modifying selected wavelet coefficients of the host image. The embedded data is encrypted by means of the Achterbahn-128 stream cipher.

The organization of this paper is as follows: in the following section we provide the main specification of Achterbahn-128. Next, we describe the wavelet transform technique. We then detail an FPGA-based implementation for this data hiding. Finally, we consider the simulation and synthesis results for our FPGA-based solution.

The main specifications of Achterbahn-128
The keystream generator of Achterbahn-128 consists of thirteen binary primitive nonlinear feedback shift registers of lengths between 21 and 33 and a Boolean combining function as shown in Fig 1 [5].

The function F combines the output sequences of the thirteen feedback shift registers to produce the keystream:

Throughout the remainder of these discussions, we shall use the capital letters Aj (j = 0,1, . . .12) to designate the primitive FSR's and – in a slight abuse of notation – also to designate the feedback functions of the shift registers. The length of the shift register Aj is denoted by Nj. We have:

Let the initial state of the shift register Aj prior to encryption be given by the row vector:

The row vector r0 is derived from the secret key K and the initial value IV using the key-loading algorithm to be described later in this paper. The key-loading algorithm ensures that r0 will not be zero vectors, irrespective as to which K–IV pair is used for initialization [5].

The output of the keystream generator at time t, denoted by S(t), is the one of the Boolean combining function F with the inputs corresponding to the output sequences of the NLFSRs correctly shifted:

1. The keystream generator of Achterbahn-128.

The key-loading algorithm
Achterbahn-128 accommodates all key lengths between 40 and 128 and all IV-lengths between 0 and 128 that are multiples of eight. We shall use the letters k and l to denote the key and IV length, respectively [5]. Assume that the secret key k is given as the bit string. . .

. . . and that the initial value (or initial vector) is given as:

The key and IV-loading algorithm is defined as follows [5]:

Step 1: The memory cells. . .

. . .of the shift register Aj are filled with the first Nj key bits:

This is done for all thirteen shift registers in the keystream generator of Achterbahn-128.

Step 2: Into each shift register Aj the remaining K – Nj key bits. . .

. . . are introduced, one after the other, according to Fig 2.

Step 3: Into each shift register Aj all l initial value bits. . .

. . . are introduced in the same way as already described for the key bits in Step 2.

Step 4: Each shift register Aj emits one bit. The thirteen shift register bits are then compressed by the Boolean combining function F into one output bit. This output bit is immediately fed back into each shift register as depicted in Fig 2. The same output bit is fed into all thirteen shift register. This operation is repeated 32 times.

Step 5: The content of the memory cell D0 in each shift register Aj is overwritten with a 1. This operation makes sure that none of the shift registers gets initialized with the all zero state.

Step 6: Each shift Aj is clocked 64 times without emitting any output bit (warm-up). The states of the shift register Aj at the end of this step define the initial state of the keystream generator.

2. Bitwise introduction of key or IV bits into a shift register.