How to simplify hardware prototyping with EXP modules

Anyone who has ever built a hardware prototype understands the challenges involved in getting a working system in place. To start, do you build your system from scratch with a custom designed board, or do you try to piece things together from existing off-the-shelf hardware components? There are obviously many factors that influence this decision, including system performance, functionality, hardware availability, engineering resources, budget, and schedule.

With the exploding use of FPGAs as main system components, combined with the plethora of FPGA development boards, the argument for using off-the-shelf components seems to make sense. The downside to this approach is that it can be difficult to find a FPGA development board that has the exact features that you might be looking for. All too often there are boards that seem to contain just about every function and interface that you can think of – except the one that you really need. And then there's the other side of the coin with regards to all of the included functions and interfaces, which is why pay for all of these extra bells and whistles if you aren't actually going to use them?

What many designers are looking for in a FPGA platform are the basic circuits to support the FPGA and something that gives them easy access to the FPGA I/Os. This way, specific functions and interfaces can be added to a standard baseboard through daughter cards or connected via cables to other existing hardware. Such a development platform offers the greatest flexibility, reduces cost, and provides the exact needs for a particular prototype setup.

The new EXP specification defines a versatile expansion interface to FPGA baseboards, allowing designers to add application-specific daughter cards and easily connect to the FPGA I/Os. With an EXP-enabled board, you can add functions from a growing list of off-the-shelf EXP modules or you can focus your efforts on building your own add-on module(s) while leveraging the existing baseboard functions. The EXP specification was developed exclusively for the unique requirements of FPGA development boards. Let's explore these requirements to better understand the advantages of the EXP specification.

Flexible I/O
Most industry standard buses – such as PCI, PMC, PCMCIA, or PC-104 – implement an address and data bus structure, which is ideal for processor-based systems. However, FPGA development boards typically do not fit this model and instead require a more generic, universal I/O structure where the user can define the I/Os as they are needed. Therefore, the EXP specification provides a great deal of flexibility by limiting the number of fixed signal definitions, allowing a more free-form I/O assignment as determined by the end-user application. The EXP specification defines a 132-pin connector, with 24 power, 24 grounds, and 84 user I/O. The standard EXP configuration uses two connectors in a dual-slot EXP configuration for a total of 168 user I/Os.

FPGAs interface to a wide range of circuits through a number of I/O standards. Supporting the nearly thirty Virtex-4 or twenty-plus Spartan-3 I/O standards is probably not realistic, but covering the popular ones is certainly desirable. The EXP specification supports the sweet spot of these standards with both single-ended and differential signaling. The specification defines four signal types: Single-Ended I/O, Differential I/O, Differential and Single-Ended Clock Inputs, and Differential and Single-Ended Clock Outputs. Table 1 shows a summary of the signal categories for the standard, dual-format EXP slot.

Table 1. Summary of signals for the standard dual-format EXP slot.

Since the FPGA I/Os can be configured for either single-ended or differential use, the differential I/Os defined in the EXP specification can actually serve a dual role. All the differential I/O signals can be configured as either differential pairs or single-ended signals, as required by the end application. In providing differential signaling, higher performance LVDS interfaces can be implemented between the baseboard and EXP module. Connection to high-speed A/Ds, D/As, and flat panel displays are possible with this signaling configuration. LVDS speeds are primarily determined by the I/O speed of the baseboard FPGA, but are also affected by the baseboard specific signal routing between the FPGA and EXP connectors. Applications that require single-ended signals only can use each differential pair as two single-ended signals, for a total of 78 single-ended I/O per connector (156 total in the dual slot configuration).

Voltage levels for the user I/Os are jumper settable on the baseboard. As a minimum, the baseboard allows for either 2.5V or 3.3V signal levels to both the single-ended and differential signals. Differential signals require the 2.5V setting, which means that – when implemented – they force the single-ended signals to the 2.5V level. For applications where all signals are single-ended, you can select between either 2.5 volts or 3.3volts.