How to get the best cost savings when implementing an FPGA-to-ASIC conversion

This article will discuss how the ASIC vendor can assist the OEM board design and FPGA design teams in "designing for portability," so that their strategies for power supplies, package types, I/O utilization, IP selection and the development of timing scripts and clocking architectures can be developed with consideration of maximizing cost reduction through conversion to ASIC. Additionally, it will discuss the strategies ASIC and structured ASIC designers should consider to assure first time success of their designs in silicon and a smooth transition from prototype approval to volume production of reliable, cost-effective devices.

No chip is an island
The old saying that "no man is an island unto himself" can be applied to electronic components also. No FPGA or ASIC has any practical function until it is connected to the broader environment of the program board and through that, to an overall system or piece of equipment. Yet it can happen that the mindset of the board-designer who develops component specifications and the FPGA or component designer who works to realize those specifications can be "insular" and focused on the task at hand, with little thought given to requirements of future cost reduction.

When such cost reduction efforts are initiated later – sometimes by other groups entirely – it is often the case that the program board and its components have gone through system qualification and are by that time "frozen," so that any replacement parts must be "footprint" as well as functionally identical. This can limit the opportunities of cost reduction an ASIC vendor can offer at that point.

By contrast, OEM board and component design teams that consider paths to eventual cost reduction early in the process, at the concept stage, can benefit by involving potential ASIC suppliers early in that process and keep them involved through completion of the board and component design phases. The advice that the ASIC vendor can offer will permit a smoother "portability" from the FPGA to a lower cost ASIC and will allow the vendor to take advantage of the most efficient design for cost reduction as regards technology, packaging and test methodology. Let's examine how this process can work.

Design for portability
Decisions made by program board and FPGA designers can impact the eventual conversion to a low cost ASIC either positively or negatively. By bringing the ASIC vendor into the process early, the ASIC vendor can assist in implementation of a "parallel design flow" (Fig 1), whereby RTL is developed and targeted to the FPGA which will also permit easy migration to an eventual ASIC. Timing scripts and clocking architectures are developed for both the FPGA and the ASIC.

1. Parallel design flow.

In general, the more synchronous the design, the more portable it is to other technology nodes. Certain design practices regarding the avoidance of gated clocks and synchronization of data transfers between clock domains can greatly enhance the portability of the FPGA to the ASIC.

Many FPGAs deliver faster clock-to-out times than are required by system performance. If the FPGA designer can document the system clock-to-out requirements for the ASIC conversion, an ASIC technology that is older than the FPGA technology may be considered, resulting in additional cost savings due to the reduced cost of silicon. Additionally, the ASIC designer may be able to reduce the I/O currents and improve board-level signal integrity.

In selecting IP for the FPGA, it is recommended to either use third-party party "soft" I/P that's portable to other technologies or to use IP supplied by the ASIC vendor (which can be more easily ported to the eventual ASIC, thus making the design as "technology independent" as possible. Using certain customized FPGA IP may impede or even prevent conversion to an ASIC.

The program board can be developed with consideration of both the large, power-hungry FPGA package and a smaller, more efficient package for the eventual ASIC (Fig 2). FPGAs use more power than an ASIC and require a higher performance package, whereas the ASIC can often utilize a lower performance industry standard package with fewer pins or ball counts and thus reduced cost.

2. Package shrink.

Additionally, the program board can be designed with an isolated power supply for the FPGA core allowing a regulator or resistor change to switch to a higher core voltage for the ASIC that may be manufactured in a less expensive technology than the FPGA.

JTAG implementation at the board level may take into consideration only the FPGA I/O that are actually utilized and which would be required for functional implementation in the corresponding cost-reduced ASIC. Otherwise, the ASIC die size (and cost) may need to grow to support all the unused I/O of the FPGA.