Reality TV for FPGA design engineers!

<Changes to whisper mode>

Our challenge tonight is from Jason "Big Idea" from marketing and sales. Our contestants are two humble and hard-working engineers, Kumar and Jane. Kumar is the ultimate seasoned engineer with a highly skeptical attitude. Jane graduated four years ago from a top engineering university and is a real go-getter.

Jason: The XV9 product was a big winner in the '90s, a real cash cow. We stopped development when we were sidetracked on all of those E-to-nowhere opportunities during the dot-com boom. Our completion date is nearly here. We need to buckle down and get this product redesigned to be competitive again and back on our distributors' shelves within six months. Your task is to upgrade the XV9 video display output to 1280 by 780 pixels and add support for a PCI Express X1 interface. In addition, if we're going to stay afloat, we need a low-risk solution with the lowest product cost increase and a low NRE cost. Again, we only have six months to complete this task.

Kumar: Unless you give us some realistic constraints, this is a farce. The XV9's main component is an ASIC using 0.35 µm technology that includes an RS-232 115K baud interface and a low-resolution video interface. Can PCI Express be supported on 0.35 µm technology? Does our ASIC vendor still support this technology? Is it available in lead-free packaging so we can continue to ship to Europe? If we have to move to a newer process technology, the NRE costs may be prohibitive. There's little chance of having this done in six months. I thought this was "America's Top Engineer," not "Candid Camera."

Jane: Sorry to disappoint you, Kumar, but we do have a solution. We can use a low-cost FPGA to replace that ASIC.

Kumar: That ASIC runs at 150 MHz. You're not going to get a FPGA design, especially a low-cost FPGA design, to run at 150 MHz. Even if you can, how can the design be converted to a FPGA and optimized using primitive, toy-like, FPGA design software? I used FPGAs on a project a few years back and timing closure was a nightmare.

Jane: Get out of the Stone Age! Low-cost FPGAs can easily run at 150 MHZ and faster, and the IP for PCI Express isn't that expensive either. To really keep the cost down, I'll propose a low-cost FPGA with an external PHY. Total solution cost is close to our ASIC pricing and we don't need to buy thousands of them at a time, so we can better manage the product life cycle going forward.

What do you think? Is this reality or just another farcical reality TV show? The fact is, this is the new reality. ASIC design starts have decreased dramatically over the last few years, while FPGA design starts are up significantly.

Few FPGA designs start from a clean slate. Most engineering teams try to reuse whatever in-house intellectual property (IP) they have, and some portion of that IP may come from an old ASIC design. In many cases, I see ASICs being completely replaced by low-cost FPGAs covering a larger density range, offering faster performance, available in lead-free packaging and being supported by ASIC class design tools without all of the headaches of ASIC design.

Before ASIC designers can consider moving an ASIC design to a low-cost FPGA, they need to be aware of the latest low-cost FPGA capabilities, have an idea of the differences between ASIC and FPGA design flows, and know the general guidelines to be followed.

What is a low-cost FPGA?
If you have not looked at low-cost FPGAs recently, you will be surprised. The latest breed of low-cost FPGA products offers customers functionality, performance, and cost characteristics that were found only in ASIC devices just a few years ago. These new FPGAs cost as little as a few dollars and offer densities spanning from a few thousand logic elements (LEs) to nearly 70,000. Low-cost FPGAs can now feature over 1 megabits of embedded memory, dedicated hardware multipliers, phase-lock loops (PLLs), support for a myriad of I/O standards, and support from ASIC-strength development software without the overhead and costs associated with ASIC development.

Switching from ASIC design to FPGA design
Although the underlying structure of FPGAs is different to ASICs, modern FPGA design software provides methodologies and features that enable ASIC designers to successfully design FPGAs with relatively high performance and much higher productivity than that offered by ASIC design flows. FPGA design software offers innovative technologies to speed system design and take advantage of the programmability of FPGAs for in-system verification.

Overview: FPGA versus ASIC design flows
FPGA design software supports the same basic design, register transfer level (RTL) synthesis, place-and-route, and verification flows used by ASIC designers. However, FPGA designs do not require some of the physical design and test design steps required for custom ASIC designs (Fig 1).

1. FPGA and ASIC design flows are fundamentally very similar.

Scan insertion and clock tree synthesis are not required in FPGA design flows. In FPGA design flows, place-and-route is performed by the customer using vendor-specific FPGA place-and-route tools. In ASIC design, place-and-route and physical design verification such as crosstalk analysis between internal device signals is either performed by the customer or handed off to an ASIC foundry for implementation.