Design Article

Multi-voltage systems need tough supervisors

Greg Sutterlin

10/10/2003 1:10 PM EDT

Multi-voltage systems need tough supervisors
The original voltage supervisors met a simple need: monitor the voltage that powered the system logic, and reset the processor following power-up or a low-voltage condition. Other functions have since been added, including watchdog timers, low-line monitors, battery switchover circuitry and chip-enable control.

As higher component density and higher processor speeds demanded lower voltages for the core supply, multivoltage systems began to appear. The first such systems were dual-voltage designs for the logic and core, but further advances in FPGAs, custom ASICs and other products added a third and sometimes a fourth voltage level. By keeping pace with the development of increasingly complex products, supervisor ICs have continued to provide the monitoring and control essential for these systems. The following discussion covers some of the latest techniques for supervising multiple voltages.

Multivoltage supervision

In multivoltage systems, the simplest way to generate a power-on-reset (POR) signal is to monitor the 3.3 V or 5 V logic supply. At power-up, when the logic voltage rises above its threshold, the supervisor initiates a reset period to ensure an orderly turn-on of the processor. As long as the processor's supply voltage is within specifications (during normal operation), the supervisor continues to monitor that voltage for transient and brown-out conditions.

But what about the integrity of devices operating at lower levels of core/supply voltage? Those levels are generated from linear or switching power supplies, so how can you assume they are within specification before the reset period has elapsed? By monitoring only a single voltage in a multivoltage design, the risk can go undetected. Improperly powered devices may be loading the bus or responding in an erratic manner, causing software to deviate from its expected procedure. A good foundation for reliable design must therefore include the ability to monitor all voltages.

Available supervisors can monitor two, three or even four supply voltages, either with factory-programmed thresholds or with a combination of factory and resistor-programmable thresholds. Factory-programmed thresholds are usually available in increments of 50 mV to 100 mV below the monitored voltage level, so a supervisor is selected according to its specified tolerance. If, for example, a supervisor family specifies thresholds of 3.3 V, 3.08 V, 2.93 V and 2.63 V, you compose a part number for the device by noting the desired voltage and its corresponding suffix.

Factory-programmed supervisors are single-chip devices that require no external components for threshold settings. The absence of resistor dividers for the thresholds also eliminates a source of power dissipation. Resistor-programmable devices, on the other hand, are suitable for engineers who want to avoid an application-specific device. Once your company qualifies a particular supervisor, you can easily change its threshold by substituting one or two resistors. And for single-supply systems, you can use the same multivoltage supervisor after disabling its other inputs.

The movement of logic levels from 5.0 V and 3.3 V toward 2.5 V and 1.8 V is creating a need for supervisors that can monitor voltages as low as 0.9 V. Such supervisors should operate directly from 1.8 V, because the higher voltage levels will not always be available. The smaller difference between active and inactive states also poses a need to maintain valid reset operation down to supply levels of 1.0 V and lower. The ability to reject short-duration transients in the supply voltage (good transient immunity) is another feature critical for low-voltage systems. Many data sheets include a graph of transient duration vs. voltage overdrive, which allows the designer to avoid nuisance resets by reviewing noise characteristics inherent in the power supply.

Current off-the-shelf supervisor ICs are extremely flexible in meeting system needs. Besides multivoltage monitoring, they offer features that make designs more robust and less susceptible to transient conditions in the hardware and software. The following considerations are critical in selecting a supervisor.

Reset period is a delay interval following the rise of all monitored voltages above their reset thresholds, during which the reset output is held low. A popular value is 140 millisecond minimum. Thus, the reset pin remains active for at least 140 ms after all monitored voltages have risen above their thresholds. Reset commands vector the software to a specific code location from which an orderly startup can be initiated.

Resets also occur in response to a low voltage, manual reset or watchdog timeout. Reset initializes the code, and thereby prevents the processor from executing code that might have been corrupted by a low voltage or software bug. If processor specifications permit, it may be more suitable to increase or decrease the reset period. Available devices provide reset periods ranging from 1 ms to 1.2 seconds.

The reset period also allows the supply voltages, crystal and phase-locked loop (PLL) to stabilize. The crystal and PLL have the largest effect on reset period duration. A 20-MHz crystal without PLL can use a short timeout, but a 32 kHz crystal phase-locked to 20 MHz with a PLL requires a longer timeout.

Watchdog timers check for proper software execution. If the software sticks in a loop caused by a bug or hardware failure, the watchdog timer resets the processor and allows it to reinitialize itself. To avoid a reset, the software must generate an edge transition at the watchdog input before the end of each timer period. An edge transition (rather than an active low or high input) removes the possibility of disabling the watchdog due to a locked processor output. You must place timer resets (edge transitions) in the software at locations that ensure a reset of the watchdog before the timeout period elapses.

The art in implementing a watchdog timer is to place the timer resets so they preclude the possibility of a stuck loop. A handy tip is to force a low-to-high transition in one routine and a high-to-low transition in the next routine in the sequence. Then, a reset will occur if the software is stuck in one of the routines. Placing a low-high-low pulse in a single subroutine does not produce a reset, so the software could remain locked.

To accommodate processors with extended power-up and stabilization requirements, some supervisors provide longer initial watchdog periods. A longer period allows the processor time to initialize and configure itself before implementing the subsequent shorter and more rigorous watchdog intervals.

Manual reset provides users and functional test devices an easily accessible means of resetting the processor. Several supervisor products provide an active-low input with internal pull-up resistor, which eliminates the need for an external resistor and also allows for a simple switch interface. Another specification associated with the manual-reset input is glitch rejection. To avoid an unintentional or nuisance reset, the input should reject short-duration glitches. Such glitch-rejection circuitry not only prevents unintentional resets, but also eliminates the need for external switch-debouncing circuitry.

Manual resets typically trigger a reset period. To reduce test time, however, the reset period should be short. MAX6390 ICs address this concern with periods about one-eighth that of a standard reset period (for a MAX6390D4, the manual reset pulse is 140 ms minimum and the reset period is 1.12 seconds).

In addition to level-sensitive manual-reset inputs, some applications may require edge-sensitive inputs, which ensure that the processor is reset for a fixed period rather than a period that depends on how long the manual-reset input is held low. That capability is handy for reducing product-assembly and test time.

For medical or safety-related equipment that performs self-testing, some supervisors can enable the detection of both overvoltage and undervoltage conditions. These devices have resistor-programmable inputs that force a reset when the monitored voltage exceeds a threshold. Like the undervoltage condition, excessive voltage can cause unexpected results in firmware as well as hardware. Forcing the processor into reset mitigates a potentially unsafe condition.

Analog-output failures can occur in a number of ways, but a simple negative voltage monitor can confirm that the expected supply voltages are present and within specification. Analog modules with 5-V or 15-V rails , for instance, often produce analog outputs for which there is no supply-voltage feedback to verify their validity. Fortunately, an overvoltage monitor can also monitor a negative voltage. As for the overvoltage case, the supply voltage is sensed by an external resistor divider between that voltage and Vcc.

To prevent latchup and to maximize reliability during power-up, a multivoltage system often includes a requirement to sequence or track the VI/O to Vcore or Vcore to VI/O voltages. Tracking generally means the I/O and core voltages must rise together, and (usually) the core voltage must not exceed the I/O voltage by more than 0.30 V. Sequencing generally means that the I/O voltage must rise before the core voltage. The system may also specify a delay period between the rise of the I/O and core voltages.

One type of sequencer for a two-voltage system (I/O = 3.3 V and core = 2.5 V) employs a single-voltage supervisor that monitors the 3.3-V supply. When that voltage is above its threshold, the supervisor delays and then enhances an external p-channel MOSFET. That approach is cost effective for low-current applications, but for higher currents the cost of a low-Rds(on) p-FET with low Vgs threshold can be high.

For higher-current applications, a dedicated power sequencer with charge pump may be more effective. As in the preceding example, this circuit monitors a supply voltage and activates an external FET to bring up the second supply. The IC device, however, allows use of an n-channel FET that costs less than the p-channel device. The internal charge pump provides a Vgs of 5.0 V, which fully enhances the n-FET powering the second supply. Not only does the n-FET cost less; its Rds(on) is notably lower.

Voltage detection

The importance of monitoring all supply voltages in a system cannot be overemphasized. It can be performed via feedback, or by a supervisor driving the reset pin of a processor. Feedback can be in the form of an A/D converter measuring system voltages, or a software routine monitoring device functionality. Either approach assures the engineer of proper power on the board.

Another simple method achieves the same result with voltage detectors. Voltage detection can be more informative than supervision, because it indicates which supply voltage has a problem. Supervision usually Ors together all voltages and generates a single reset, whereas a multivoltage detector usually offers open-drain outputs that can be reviewed individually to determine the source of the problem. Quad-voltage monitors are available with independent open-drain outputs. Such devices can include resistor-programmable thresholds as well as factory-programmed thresholds that accommodate supply voltages of 1.8 V, 2.5 V, 3.3 V, 5.0 V, or 5.0 V. An internal precision voltage reference and internal voltage dividers make these ICs very compact.

Greg Sutterlin is applications manager at Maxim Integrated Products Inc. (Sunnyvale, Calif.).





Please sign in to post comment

Navigate to related information

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)

Feedback Form